Patents by Inventor Masahiko Saitou

Masahiko Saitou has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7065282
    Abstract: In a holder and a structure for organizing excess length by winding cables and the like, an excess length organizing holder comprises a baseboard which has a rotation axis vertical to a fixed plane, and a spool which has a flange whose edge is provided with two incisions and a winding portion. The spool is rotated around the rotation axis in a state where a cable is folded by way of the winding portion and the two incisions, thereby winding the cable twofold around the winding portion. Also, an excess length organizing structure comprises a door detachable from a box-shaped rack, a mounting hardware connecting the door to the rack and pivoting on one side so as to make the door openable and closable, and at least one excess length organizing holder mentioned above whose baseboard is attached on a surface of the door when the door is attached to the mounting hardware.
    Type: Grant
    Filed: November 17, 2004
    Date of Patent: June 20, 2006
    Assignee: Fujitsu Limited
    Inventors: Koji Sasaki, Jun Sakiura, Masahiko Saitou, Kenji Joko, Hideaki Matsumoto
  • Publication number: 20060045458
    Abstract: In a holder and a structure for organizing excess length by winding cables and the like, an excess length organizing holder comprises a baseboard which has a rotation axis vertical to a fixed plane, and a spool which has a flange whose edge is provided with two incisions and a winding portion. The spool is rotated around the rotation axis in a state where a cable is folded by way of the winding portion and the two incisions, thereby winding the cable twofold around the winding portion. Also, an excess length organizing structure comprises a door detachable from a box-shaped rack, a mounting hardware connecting the door to the rack and pivoting on one side so as to make the door openable and closable, and at least one excess length organizing holder mentioned above whose baseboard is attached on a surface of the door when the door is attached to the mounting hardware.
    Type: Application
    Filed: November 17, 2004
    Publication date: March 2, 2006
    Inventors: Koji Sasaki, Jun Sakiura, Masahiko Saitou, Kenji Joko, Hideaki Matsumoto
  • Patent number: 6907555
    Abstract: The present invention is a self-test circuit (BIST) incorporated in the memory device, which is activated in response to a test activation signal from outside. When this self-test circuit is activated in response to a test activation signal (WBIZ) from outside, it generates a test operation command (WBI-CMD), generates a test address (WBI-ADD), and generates test data (WBI-DATA). Furthermore, after the self-test circuit writes the test data to a memory cell, it effects a comparison to establish whether or not the read data that is read from this memory cell is the same as the test data that was written thereto and stores information as to the result of this comparison. This comparison result information is then output to the outside.
    Type: Grant
    Filed: October 19, 2000
    Date of Patent: June 14, 2005
    Assignee: Fujitsu Limited
    Inventors: Yukihiro Nomura, Hiroyuki Fujimoto, Takahiro Suzuki, Tatsuya Kanda, Yasurou Matsuzaki, Masahiko Saitou, Hiroyoshi Tomita
  • Patent number: 6707323
    Abstract: There is provided a semiconductor device having an output circuit for outputting a predetermined signal, and an output-level adjusting circuit for adjusting an output level of the output circuit in response to an adjustment start signal externally supplied and outputting an adjustment end signal upon completion of adjustment. A module in which a plurality of the semiconductor devices above are mounted. The module has an adjustment-start-signal terminal for receiving the adjustment start signal externally supplied and supplying the adjustment start signal to the semiconductor devices, and an adjustment-end-signal terminal for outputting a module adjustment end signal in response to adjustment end signals from the semiconductor devices. A plurality of such modules can be mounted in such a way that the adjustment-end-signal terminal of the (N−1)-th module is connected to the adjustment-start-signal terminal of the N-th module.
    Type: Grant
    Filed: September 21, 2000
    Date of Patent: March 16, 2004
    Assignee: Fujitsu Limited
    Inventors: Yasurou Matsuzaki, Masahiko Saitou