Abstract: A dual-port memory is provided between an internal bus of a control unit of an exchange and a general-purpose bus such as an ISA bus or a PCI bus. A LAN controller for connecting to a LAN and a processor controller for controlling the LAN controller are connected to the general-purpose bus. In a configuration where a plurality of application processors are connected to the LAN, software for implementing a server function for enabling the application processors to be clients and a gateway function for connecting the LAN to the internal bus of the exchange is downloaded into the processor controller. In a configuration where a centralized management console is connected to the LAN, software for implementing an SNMP agent function is downloaded into the processor controller.

Abstract: The present invention incorporates a control mechanism in an input buffer for a gate array so that the input buffer may be directly enabled or disabled by a control signal. Hence, no power will be wasted by the unnecessary operation of gates internal to the input buffer or subsequent stages. The method of control is to couple a common control signal to one input port of each of a plurality of two-input AND gates and couple an incoming data signal to the other input port of each of the two-input AND gates. The AND gates function as input buffers and the outputs of the AND gates are applied to the subsequent stage (e.g., a gate array). Thus, a LOW control signal disables the AND gate input buffers and subsequent stages coupled to the outputs of the AND gates, regardless of whether the incoming data signals are of a HIGH or LOW state.