Abstract: A process for fabricating a micro-electro-mechanical system (MEMS) composed of fixed components fixedly supported on a lower substrate and movable components movably supported on the lower substrate. The process utilizes an upper substrate separate from the lower substrate. The upper substrate is selectively etched in its top layer to form therein a plurality of posts which project commonly from a bottom layer of the upper substrate. The posts include the fixed components to be fixed to the lower substrate and the movable components which are resiliently supported only to one or more of the fixed components to be movable relative to the fixed components. The lower substrate is formed in its top surface with at least one recess. The upper substrate is then bonded to the top of the lower substrate upside down in such a manner as to place the fixed components directly on the lower substrate and to place the movable components upwardly of the recess.

Abstract: A process for fabricating a micro-electro-mechanical system (MEMS) composed of fixed components fixedly supported on a lower substrate and movable components movably supported on the lower substrate. The process utilizes an upper substrate separate from the lower substrate. The upper substrate is selectively etched in its top layer to form therein a plurality of posts which project commonly from a bottom layer of the upper substrate. The posts include the fixed components to be fixed to the lower substrate and the movable components which are resiliently supported only to one or more of the fixed components to be movable relative to the fixed components. The lower substrate is formed in its top surface with at least one recess. The upper substrate is then bonded to the top of the lower substrate upside down in such a manner as to place the fixed components directly on the lower substrate and to place the movable components upwardly of the recess.

Abstract: A solid state relay composed of a series connected pair of LDMOSFETs has a minimized output capacitance. Each LDMOSFET is configured to have a silicon layer of a first conductive type, a drain region of the first conductive type diffused in the top surface of the silicon layer, a well region of a second conductive type diffused in the silicon layer in a laterally spaced relation from the drain region, and a source region of the first conductive type diffused within the well region to define a channel extending between the source region and a confronting edge of the well region along the top surface of the silicon layer. Each LDMOSFET is of an SOI (Silicon-On-Insulator) structure composed of a silicon substrate placed on a supporting plate, a buried oxide layer on the silicon substrate, and the silicon layer on the buried oxide layer.

Abstract: To provide a semiconductor device having a large allowable current, a demanded withstand voltage, and small output capacitance and resistance, the semiconductor device comprises a semiconductor layer formed on a semiconductor substrate, and the semiconductor layer includes a first conductivity type-drain region, a second conductivity type-well region apart from the drain region, a first conductivity type-source region in the well region apart from one end of the well region on the side of the drain region, a first conductivity type-drift region formed between one end of the well region and the drain region and in contact with the well region and the drain region, respectively, and a gate electrode formed spaced a gate oxide layer and on the well region located between the drift region and the source region; and the impurity concentration of the drift region decreases in the lateral direction and also in the vertical direction, respectively, as the distance from the drain region increases.

Abstract: A solid state relay composed of a series connected pair of LDMOSFETs has a minimized output capacitance. Each LDMOSFET is configured to have a silicon layer of a first conductive type, a drain region of the first conductive type diffused in the top surface of the silicon layer, a well region of a second conductive type diffused in the silicon layer in a laterally spaced relation from the drain region, and a source region of the first conductive type diffused within the well region to define a channel extending between the source region and a confronting edge of the well region along the top surface of the silicon layer. Each LDMOSFET is of an SOI (Silicon-On-Insulator) structure composed of a silicon substrate placed on a supporting plate, a buried oxide layer on the silicon substrate, and the silicon layer on the buried oxide layer.

Abstract: To provide a semiconductor device having a large allowable current, a demanded withstand voltage, and small output capacitance and resistance, the semiconductor device comprises a semiconductor layer formed on a semiconductor substrate, and the semiconductor layer includes a first conductivity type-drain region, a second conductivity type-well region apart from the drain region, a first conductivity type-source region in the well region apart from one end of the well region on the side of the drain region, a first conductivity type-drift region formed between one end of the well region and the drain region and in contact with the well region and the drain region, respectively, and a gate electrode formed spaced a gate oxide layer and on the well region located between the drift region and the source region; and the impurity concentration of the drift region decreases in the lateral direction and also in the vertical direction, respectively, as the distance from the drain region increases.

Abstract: A solid state relay composed of a series connected pair of LDMOSFETs has a minimized output capacitance. Each LDMOSFET is configured to have a silicon layer of a first conductive type, a drain region of the first conductive type diffused in the top surface of the silicon layer, a well region of a second conductive type diffused in the silicon layer in a laterally spaced relation from the drain region, and a source region of the first conductive type diffused within the well region to define a channel extending between the source region and a confronting edge of the well region along the top surface of the silicon layer. Each LDMOSFET is of an SOI (Silicon-On-Insulator) structure composed of a silicon substrate placed on a supporting plate, a buried oxide layer on the silicon substrate, and the silicon layer on the buried oxide layer.

Abstract: A thin film transistor of SOI (Silicon-On-Insulator) type includes a buried oxide layer formed on a semiconductor substrate, a silicon layer of a first conductive type formed on the buried oxide layer, and an upper oxide layer formed on the silicon layer. The silicon layer has a body region of a second conductive type, source region of the first conductive type, drain region of the first conductive type, and a drift region of the first conductive type. The silicon layer is formed with a first portion of a thickness T1 in which the doping region is formed, and a second portion of a thickness T2 in which the body region is formed to reach the buried oxide layer. When the thicknesses T1 and T2 are determined so as to satisfy the relationships:0.4 .mu.m<T1,0.4 .mu.m.ltoreq.T2.ltoreq.1.5 .mu.m, andT2<T1,The transistor exhibits an improved power dissipation, high breakdown voltage, and a low on-resistance, and also provides advantages in a manufacturing process of the transistor.

Abstract: A method for manufacturing a static induction type semiconductor device is to form gate zones on a surface side of a semiconductor substrate, to cover the surface including the gate zones with an oxide film, to form through the oxide film apertures for providing cathode zones in the substrate, the apertures respectively overlapping partly each gate zone, and to form the cathode zones with thermal diffusion of an impurity carried out through the apertures, the cathode zones thus partly overlapping the gate zones. Concentration of the impurity as well as the depth of the diffusion at thus made impurity diffusion zones can be thereby stabilized, and eventually electric characteristics of enhancement type, static induction type semiconductor device can be sufficiently made stable.

Abstract: A double-diffused metal-oxide-semiconductor field effect transistor (DMOSFET) device comprising an insulating layer having an opening on the top surface of a semiconductor wafer, channel regions and well regions and source regions formed through two stage deffusions of impurity materials respectively of a different conductivity type from and the same conductivity type as the wafer and carried out through the opening, and further comprising gate, source and drain electrodes which are formed after mashes provided on a surface area where the drain regions and the source electrode regions that are to be connected to the well regions and source regions and a further ion-implantation of an impurity material of the same conductivity type as the wafer into the channel regions, with the threshold voltage controlled to achieve a depletion type.

Abstract: A method for manufacturing double-diffused metal-oxide-semiconductor field effect transistor (DMOSFET) device is to form an insulating layer having an opening in top surface on a semiconductor wafer, channel regions and well regions and source regions through two stage diffusions of impurity materials respectively of a different conductivity type from and the same conductivity type as the wafer and carried out through the opening, and further gate, source and drain electrodes are formed after masks provided on a surface area where the drain regions and the source electrode regions that are to be connected to the well regions and source regions and a further ion-implantation of an impurity material of the same conductivity type as the wafer into the channel regions, with the threshold voltage controlled to achieve a depletion type.