Abstract: A display area in a liquid crystal display apparatus is divided into five blocks extending in the lateral direction, is controlled to have a black writing period, a video writing period and a video holding period in each block in this order, and is controlled to delay the video writing period of the kth block in comparison with the video writing period in the (k?1)th block by a predetermined time period.

Abstract: A liquid crystal display device comprises a liquid crystal display panel including a liquid crystal layer for a display in an OCB mode, a heating unit which heats the liquid crystal display panel, a temperature detecting unit for detecting a temperature of the liquid crystal display panel, a time measuring unit which measures a heating time that the heating unit has operated, and a transfer drive circuit which applies a transfer drive voltage to the liquid crystal layer to transfer the alignment state of liquid crystal molecules from a splay alignment to a bend alignment in advance. The transfer drive circuit is configured to determine a transfer time as an application period of the transfer drive voltage on the basis of a relationship between the heating time and temperature which are obtained from the time measuring unit and temperature detecting unit at a desired timing.

Abstract: A liquid crystal display device comprises an OCB-mode liquid crystal display panel including a liquid crystal layer in which the alignment state of liquid crystal molecules is transitioned in advance from a splay alignment to a bend alignment, and a display control section which applies a liquid crystal drive voltage to the liquid crystal layer according to a video signal. The display control section is configured to detect the application environment of the liquid crystal display panel and determine a minimum value of the liquid crystal drive voltage based on a phase-transition threshold voltage which causes energy of the splay alignment and energy of the bend alignment to be balanced with each other in the detected application environment.

Abstract: A gate line driving circuit includes a shift register section that selects gate lines for gradation display and for black insertion, and an output circuit that outputs a driving signal to the gate line which is selected by the shift register section. In particular, the output circuit is configured to obtain an overlap between an output period of a driving signal to each selected gate line and an output period of a driving signal to a gate line that is driven in precedence to the selected gate line, and independently control a first preliminary driving period corresponding to the overlap for gradation display and a second preliminary driving period corresponding to the overlap for black insertion.

Abstract: A gate line driving circuit includes a shift register section that selects gate lines for gradation display in units of one gate line, and selects the gate lines for black insertion in units of a group including at least two adjacent gate lines, and an output circuit that outputs driving signals to the gate lines selected by the shift register section. In particular, the output circuit is configured such that an output period of a driving signal to an odd-numbered gate line, which is included in the group selected for black insertion by the shift register section and extends along a row of liquid crystal pixels that are capacitive-coupled to a non-selected gate line other than the gate lines of the group, is set to be shorter than an output period of a driving signal to an even-numbered gate line of the group.

Abstract: A gate line driving circuit includes a plurality of OR gate circuits which selects each of at least two groups obtained by dividing gate lines, and a level shifter which outputs driving signals to the gate lines of a group that is selected by the OR gate circuits. The OR gate circuits are configured such that the groups of gate lines are selected at different timings in an initialization for transferring the OCB liquid crystal pixels from a splay alignment to a bend alignment upon supply of power.

Abstract: A gate line driving circuit includes a shift register for gradation display, which shifts a first start signal in response to a first clock signal such that the gate lines are selected for gradation display in one vertical scanning period, and a shift register for black insertion, which shifts a second start signal in response to a second clock signal synchronous with the first clock signal such that the gate lines are selected for black insertion in a period substantially equal to the vertical scanning period, and an output circuit that outputs, under control of a first output enable signal, a driving signal to the gate line selected by the shift register for gradation display, and outputs, under control of a second output enable signal, a driving signal to the gate line selected by the shift register for black insertion.

Abstract: A liquid crystal display device comprises a liquid crystal display panel including a liquid crystal layer for a display in an OCB mode, a heating unit which heats the liquid crystal display panel, a temperature detecting unit for detecting a temperature of the liquid crystal display panel, a time measuring unit which measures a heating time that the heating unit has operated, and a transfer drive circuit which applies a transfer drive voltage to the liquid crystal layer to transfer the alignment state of liquid crystal molecules from a splay alignment to a bend alignment in advance. The transfer drive circuit is configured to determine a transfer time as an application period of the transfer drive voltage on the basis of a relationship between the heating time and temperature which are obtained from the time measuring unit and temperature detecting unit at a desired timing.

Abstract: The liquid crystal display device includes a liquid crystal display panel provided with source signal lines and gate signal lines arranged in matrix form and liquid crystal display elements using OCB mode liquid crystal provided at intersections between the source signal lines and gate signal lines, a gate driver which supplies a gate signal to the gate signal lines and a source driver which supplies a voltage corresponding to gradation of the display data to the source signal lines during a display period and supplies a voltage to prevent counter-transfer to the source signal lines during a counter-transfer prevention drive period, and the source driver supplies a voltage lower by a predetermined value than the voltage corresponding to the black color as the voltage to prevent counter-transfer.