Patents by Inventor Masahiko Takeuchi

Masahiko Takeuchi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6780549
    Abstract: This invention relates to a photo- or heat-curable resin composition which yields a cured product with minimal cracking and high reliability. The resin composition of this invention comprises 100 parts by weight of the resin-forming component containing a photo- or heat-polymerizable unsaturated compound and 0.01-5 parts by weight of an inorganic filler such as silica sol with its average particle diameter controlled in the range 5 nm-0.5 &mgr;m. The composition exhibits high heat resistance and good microfabrication quality and is useful as a peripheral material of electronic parts such as semiconductor devices by the build-up process, for example, as a material for forming insulation layers in multilayer printed wiring boards.
    Type: Grant
    Filed: August 22, 2001
    Date of Patent: August 24, 2004
    Assignee: Nippon Steel Chemical Co., Ltd.
    Inventors: Masahiko Takeuchi, Kazuhiko Mizuuchi, Hironobu Kawasato
  • Publication number: 20040152297
    Abstract: A method of manufacturing a semiconductor device includes the steps of: forming an interlayer insulating film covering an upper side of a projected gate portion and a gap between the projected gate portions; forming a contact hole reaching a first bottom portion introduced into a semiconductor substrate, from an upper surface of the interlayer insulating film through the gap between the projected gate portions; forming a second bottom portion having the semiconductor substrate exposed on the bottom face and the side face by forming a diffusion prevention film covering a side face of the first bottom portion and by etching further the bottom face of the first bottom portion; and forming a plug by filling the contact hole with polysilicon having an impurity doped.
    Type: Application
    Filed: July 22, 2003
    Publication date: August 5, 2004
    Applicant: RENESAS TECHNOLOGY CORP.
    Inventors: Kenichi Ooto, Masahiko Takeuchi, Yoshinori Tanaka
  • Patent number: 6770421
    Abstract: This invention relates to a photo- or heat-curable resin composition which yields a cured product with minimal cracking and high reliability. The resin composition of this invention comprises 100 parts by weight of (A) photo- or heat-polymerizable unsaturated compound composed of a polycarboxylic acid adduct of bisphenol-epoxy (meth)acrylate, 10-100 parts by weight of (B) alkylene oxide-modified product of (meth)acrylate or oligomers thereof, 0-50 parts by weight of (C) compound containing epoxy group and 0-50 parts by weight of (D) photopolymerization initiator or sensitizer. The composition exhibits high heat resistance and good microfabrication quality and is useful as a peripheral material of electronic parts such as semiconductor devices by the build-up process, for example, as a material for forming insulation layers in multilayer printed wiring boards.
    Type: Grant
    Filed: November 30, 2001
    Date of Patent: August 3, 2004
    Assignee: Nippon Steel Chemical, Co., Ltd
    Inventors: Masahiko Takeuchi, Kazuhiko Mizuuchi, Hironobu Kawasato
  • Patent number: 6765256
    Abstract: A semiconductor device includes: lower storage node electrodes provided on a main surface of a silicon substrate; a dielectric film provided on the lower storage node electrodes; an upper cell plate electrode provided on the dielectric film; and an interlayer insulating film covering the upper cell plate electrode. The upper cell plate electrode contains ruthenium. The interlayer insulating film has a contact hole reaching the upper cell plate electrode. The contact hole is provided so that the distance between the main surface of the silicon substrate and the bottom face of the contact hole is not less than the distance between the main surface of the silicon substrate and the bottom face of the upper cell plate electrode. A semiconductor device is provided wherein contact defects in the upper electrode and the generation of an area penalty are prevented.
    Type: Grant
    Filed: February 24, 2003
    Date of Patent: July 20, 2004
    Assignee: Renesas Technology Corp.
    Inventors: Masahiko Takeuchi, Takashi Dokan
  • Publication number: 20040108534
    Abstract: A storage node in a capacitor of a semiconductor device is formed of: an inner conductor in a columnar form having bottom, side and top surfaces; and an outer conductor, located on the bottom (between the bottom surface and the semiconductor substrate), side and top surfaces of the inner conductor, having a different material from that of the inner conductor. The outer conductor is formed of a metal film such as of Ru having a film thickness of about 40 nm to 80 nm. The inner conductor is formed of a film, such as a TiN film, a TaN film, a WN film or the like, having a high adhesion to the metal film such as of Ru. With this configuration, it is possible to provide a semiconductor device provided with a capacitor of which the capacitance is obtained.
    Type: Application
    Filed: June 6, 2003
    Publication date: June 10, 2004
    Applicant: Renesas Technology Corp.
    Inventors: Takaaki Tsunomura, Masahiko Takeuchi
  • Patent number: 6743692
    Abstract: It is an object to provide a technique for reducing an electric resistance between a contact plug and an impurity region to be electrically connected thereto while maintaining an insulating property between a gate electrode and the contact plug. A sidewall insulating film (17) is formed on a side surface of a gate structure (60) provided on a semiconductor substrate (1), and epitaxial layers (19a) and (19b) are formed in self-alignment on n-type impurity regions (13a) and (13b) so that the sidewall insulating film (17) lies between the epitaxial layers (19a) and (19b) and a gate electrode (50). An etching blocking film (20) and an interlayer insulating film (21) are formed over a whole surface in this order. Using the etching blocking film (20) as an etching stopper, the interlayer insulating film (21) is etched and the exposed etching blocking film (20) is subsequently etched. Consequently, contact holes (30a) and (30b) reaching the epitaxial layers (19a) and (19b) are formed.
    Type: Grant
    Filed: March 11, 2003
    Date of Patent: June 1, 2004
    Assignee: Renesas Technology Corp.
    Inventors: Shigeru Shiratake, Masahiko Takeuchi
  • Publication number: 20040089891
    Abstract: A lower electrode (11) formed of ruthenium has an opening generated by a void at time of formation, for example. A ruthenium oxide film (14) is provided on an upper surface of the lower electrode (11) to close an entry of the opening, and is formed by oxidizing the lower electrode (11). Similarly, a ruthenium oxide film (841) is provided to close an entry of an opening of a plug body (81) formed of ruthenium.
    Type: Application
    Filed: September 10, 2003
    Publication date: May 13, 2004
    Applicant: Renesas Technology Corp.
    Inventors: Masatoshi Anma, Masahiko Takeuchi
  • Patent number: 6734481
    Abstract: Lead interconnection layers and are electrically connected to the respective source and drain regions of a pair of a monitor transistor MT. Lead interconnection layers and are both formed on same insulating layer and on same insulating layer as is a bit line conductive layer of a memory cell area. Furthermore, lead interconnection layers and have respective contact sections each with a large width and to each of which a needle of a probe can be connected externally. With such a structure adopted, there can be obtained a semiconductor device capable of monitoring a transistor characteristic correctly and easily by reducing parasitic resistance, further, at an early stage in a wafer process; and a fabrication process therefor.
    Type: Grant
    Filed: April 16, 2002
    Date of Patent: May 11, 2004
    Assignee: Renesas Technology Corp.
    Inventor: Masahiko Takeuchi
  • Publication number: 20040063313
    Abstract: It is an object to provide a technique for reducing an electric resistance between a contact plug and an impurity region to be electrically connected thereto while maintaining an insulating property between a gate electrode and the contact plug. A sidewall insulating film (17) is formed on a side surface of a gate structure (60) provided on a semiconductor substrate (1), and epitaxial layers (19a) and (19b) are formed in self-alignment on n-type impurity regions (13a) and (13b) so that the sidewall insulating film (17) lies between the epitaxial layers (19a) and (19b) and a gate electrode (50). An etching blocking film (20) and an interlayer insulating film (21) are formed over a whole surface in this order. Using the etching blocking film (20) as an etching stopper, the interlayer insulating film (21) is etched and the exposed etching blocking film (20) is subsequently etched. Consequently, contact holes (30a) and (30b) reaching the epitaxial layers (19a) and (19b) are formed.
    Type: Application
    Filed: March 11, 2003
    Publication date: April 1, 2004
    Applicant: MITSUBISHI DENKI KABUSHIKI KAISHA
    Inventors: Shigeru Shiratake, Masahiko Takeuchi
  • Publication number: 20040056282
    Abstract: A semiconductor device includes: lower storage node electrodes provided on a main surface of a silicon substrate; a dielectric film provided on the lower storage node electrodes; an upper cell plate electrode provided on the dielectric film; and an interlayer insulating film covering the upper cell plate electrode. The upper cell plate electrode contains ruthenium. The interlayer insulating film has a contact hole reaching the upper cell plate electrode. The contact hole is provided so that the distance between the main surface of the silicon substrate and the bottom face of the contact hole is not less than the distance between the main surface of the silicon substrate and the bottom face of the upper cell plate electrode. A semiconductor device is provided wherein contact defects in the upper electrode and the generation of an area penalty are prevented.
    Type: Application
    Filed: February 24, 2003
    Publication date: March 25, 2004
    Applicant: MITSUBISHI DENKI KABUSHIKI KAISHA
    Inventors: Masahiko Takeuchi, Takashi Dokan
  • Patent number: 6684627
    Abstract: The present invention is a method of solidifying sulfur component being the cause of “SOx poisoning” by use of a sulfur solidifier. The solidifier includes a metal element having a function of oxidizing the sulfur component and a basic metal element. And the solidifier solidifies sulfur component before exhaust gas flows into an NOx-occluding reduction-type exhaust purifying catalyst located on an exhaust path. Since the foregoing sulfur solidifier includes the above metal element and the basic metal element, it can effectively solidify the sulfur component which are the cause of the SOx poisoning, and ensure improvement in purification performance.
    Type: Grant
    Filed: May 21, 2001
    Date of Patent: February 3, 2004
    Assignee: Toyota Jidosha Kabushiki Kaisha
    Inventors: Tatsuji Mizuno, Shinji Tsuji, Masahiko Takeuchi, Kenji Kato, Takaaki Ito, Yoshitsugu Ogura, Tetsuo Kawamura, Mareo Kimura
  • Patent number: 6591576
    Abstract: A structural member having a closed section, and an apparatus and a method for producing the same are provided to decrease production costs and secure the dimensional accuracy by a simple construction. The apparatus produces a structural member provided with a channel-shaped sectional portion and closed sectional portions adjacent thereto by bending a work and includes a press mold formed of a punch and a die oppositely installed and used for press-forming so that both side edges of the work are caused to overlap on the bottom wall of the channel-shaped sectional portion, and a fall-down prevention means which prevents both side edges opposed to each other of the work to be press-formed in the press mold from falling down and guides both side edges so that the end faces thereof are brought into contact with each other.
    Type: Grant
    Filed: September 20, 2000
    Date of Patent: July 15, 2003
    Assignee: Toyota Jidosha Kabushiki Kaisha
    Inventors: Masataka Iida, Masahiko Takeuchi, Sadao Ishihara, Takanori Matsukura, Takayuki Furuhata
  • Publication number: 20030102623
    Abstract: A paper feeding apparatus includes a first support member for supporting a central area of a lower surface of printing paper placed on a paper tray, second support members for supporting corner areas of the lower surface of the printing paper, sensors for detecting heights of an upper surface of the printing paper placed on the paper tray, motors rotatable based on signals from the sensors, and lift screws vertically movable by the motors. The second support members are connected to the lift screws to be vertically movable therewith, respectively.
    Type: Application
    Filed: December 4, 2002
    Publication date: June 5, 2003
    Applicant: DAINIPPON SCREEN MFG. CO., LTD.
    Inventors: Keisuke Hirai, Masahiko Takeuchi
  • Patent number: 6569803
    Abstract: A catalyst, for purifying an exhaust gas, contains at least one catalyst component from among Pt, Pd, Rh, Au, Ag and Ir, and a complex oxide of the perovskite type comprising at least two different metal elements. In the catalyst, the catalyst component is carried on the complex oxide.
    Type: Grant
    Filed: January 16, 2001
    Date of Patent: May 27, 2003
    Assignee: Toyota Jidosha Kabushiki Kaisha
    Inventor: Masahiko Takeuchi
  • Patent number: 6521933
    Abstract: In the drawn-out interconnection structure of the present invention, a storage node (SN) groove extending from a region, and a groove-shape drawn-out electrode is formed on the inner wall of storage node (SN) groove. An extended pad electrode portion extending from groove-shape drawn-out electrode is provided above storage node (SN) groove. Also provided is a contact plug that penetrates through extended pad electrode portion and that connects aluminum interconnection and extended pad electrode portion in a layer above extended pad electrode portion. With this arrangement, the structure of an interconnection drawn from an electrode of a semiconductor device can be obtained which allows the production of a cell transistor TEG capable of performing a reliable and stable measurement of the cell transistor characteristics.
    Type: Grant
    Filed: November 30, 2000
    Date of Patent: February 18, 2003
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Takashi Miyajima, Masahiko Takeuchi
  • Publication number: 20030001179
    Abstract: Lead interconnection layers and are electrically connected to the respective source and drain regions of a pair of a monitor transistor MT. Lead interconnection layers and are both formed on same insulating layer and on same insulating layer as is a bit line conductive layer of a memory cell area. Furthermore, lead interconnection layers and have respective contact sections each with a large width and to each of which a needle of a probe can be connected externally. With such a structure adopted, there can be obtained a semiconductor device capable of monitoring a transistor characteristic correctly and easily by reducing parasitic resistance, further, at an early stage in a wafer process; and a fabrication process therefor.
    Type: Application
    Filed: April 16, 2002
    Publication date: January 2, 2003
    Applicant: Mitsubishi Denki Kabushiki Kaisha
    Inventor: Masahiko Takeuchi
  • Patent number: 6487468
    Abstract: In a forging process analyzing method, many trace points are set in a workpiece. Lines connecting the trace points express fiber flow lines. The fiber flow lines may be imaginary ones that are irrelevant to real fiber flow lines. By applying a technique of a finite element method to the fiber flow lines, deformation calculation is performed. A new trace point is added between trace points when the distance therebetween is great. The velocity of each trace point cause by deformation is calculated, and the position of each trace point is updated. When any trace point in an element is left behind in a die, the left-behind phenomenon is prevented by converting the shape of the element while the crossing of fiber flow lines is prevented. A radius is set for each trace point. The radius of each trace point is adjusted so as to eliminate off-boundary extension and overlap of fiber flow lines.
    Type: Grant
    Filed: October 28, 1999
    Date of Patent: November 26, 2002
    Assignees: Toyota Jidosha Kabushiki Kaisha, Kabushiki Kaisha Toyota Chuo Kenkyusho
    Inventors: Yoshitaka Atsumi, Naoki Matsuoka, Tadao Akashi, Hiroshi Yano, Masahiko Takeuchi, Kokichi Nakanishi
  • Publication number: 20020111278
    Abstract: An aqueous lubricant is provided which by simple application onto metal surfaces forms lubricating films required for heavy working of metals, and which contains no oil. The aqueous lubricant is prepared by suspending or dispersing a metal chelate compound in water with a surfactant or the like. The metal chelate compound has a polydentate or multidentate chelate ligand, in which at least one of the coordinating atoms is sulfur, coordinated to the coordination site of at least one metal species selected from among zinc, manganese, iron, molybdenum, tin and antimony. When applied onto metal surfaces, the aqueous lubricant forms effective lubricating films on the metal surfaces. The lubricating films contain sulfur as coordinating atoms and therefore, extreme pressure produces sulfur radicals through decomposition by tribo-chemical reactions. The sulfur radicals are highly reactive and react rapidly with the metal surface to produce metal sulfides with a lubricating effect.
    Type: Application
    Filed: November 19, 2001
    Publication date: August 15, 2002
    Inventors: Heijiro Ojima, Masahiko Takeuchi, Fumio Ikesue, Noritoshi Kashimura, Fumio Kawahara, Mitsuru Tomono
  • Publication number: 20020103270
    Abstract: This invention relates to a photo- or heat-curable resin composition which yields a cured product with minimal cracking and high reliability. The resin composition of this invention comprises 100 parts by weight of (A) photo- or heat-polymerizable unsaturated compound composed of a polycarboxylic acid adduct of bisphenol-epoxy (meth)acrylate , 10-100 parts by weight of (B) alkylene oxide-modified product of (meth)acrylate or oligomers thereof, 0-50 parts by weight of (C) compound containing epoxy group and 0-50 parts by weight of (D) photopolymerization initiator or sensitizer. The composition exhibits high heat resistance and good microfabrication quality and is useful as a peripheral material of electronic parts such as semiconductor devices by the build-up process, for example, as a material for forming insulation layers in multilayer printed wiring boards.
    Type: Application
    Filed: November 30, 2001
    Publication date: August 1, 2002
    Inventors: Masahiko Takeuchi, Kazuhiko Mizuuchi, Hironobu Kawasato
  • Publication number: 20020051942
    Abstract: This invention relates to a photo- or heat-curable resin composition which yields a cured product with minimal cracking and high reliability. The resin composition of this invention comprises 100 parts by weight of the resin-forming component containing a photo- or heat-polymerizable unsaturated compound and 0.01-5 parts by weight of an inorganic filler such as silica sol with its average particle diameter controlled in the range 5 nm-0.5 &mgr;m. The composition exhibits high heat resistance and good microfabrication quality and is useful as a peripheral material of electronic parts such as semiconductor devices by the build-up process, for example, as a material for forming insulation layers in multilayer printed wiring boards.
    Type: Application
    Filed: August 22, 2001
    Publication date: May 2, 2002
    Inventors: Masahiko Takeuchi, Kazuhiko Mizuuchi, Hironobu Kawasato