Abstract: A semiconductor switch is configured to conduct or cutoff a signal path from its first terminal to its second terminal. An enhancement-type first transistor is arranged between the first terminal and the second terminal. A first bias circuit is connected to apply a gate voltage VG that corresponds to a control signal VCNT to the gate of the first transistor when the power supply voltages VDD and VSS are supplied. A second bias circuit is connected such that a voltage that corresponds to the lower voltage of the voltages at the first terminal and the second terminal is applied to the gate of the first transistor when the power supply voltages VDD and VSS are not supplied.

Abstract: A semiconductor switch is configured to conduct or cutoff a signal path from its first terminal to its second terminal. An enhancement-type first transistor is arranged between the first terminal and the second terminal. A first bias circuit is connected to apply a gate voltage VG that corresponds to a control signal VCNT to the gate of the first transistor when the power supply voltages VDD and VSS are supplied. A second bias circuit is connected such that a voltage that corresponds to the lower voltage of the voltages at the first terminal and the second terminal is applied to the gate of the first transistor when the power supply voltages VDD and VSS are not supplied.

Abstract: There is provided a semiconductor switch apparatus that can handle a wide range of input voltages. The switch apparatus includes a main switch that is provided between a first terminal and a second terminal, and a switch controller that, to turn on the main switch, supplies the same gate-source voltage to the main switch irrespective of a direction of a current flowing through the main switch. To turn on the main switch, the switch controller supplies the gate-source voltage that is determined based on at least one of a voltage of the first terminal and a voltage of the second terminal to a gate of the main switch.

Abstract: Provided is a test apparatus, a switch apparatus, and a drive circuit comprising a current source having one end thereof connected to a reference potential; a first switch connected between the current source and a first voltage source that outputs a first power supply voltage; a first output terminal that outputs a voltage between the first switch and the first voltage source; a power supply section that outputs a second power supply voltage when the first switch is ON and outputs a third power supply voltage, which is lower than the second power supply voltage, when the first switch is OFF; a second switch connected between the power supply section and the current source; and a second output terminal that outputs a voltage between the second switch and the power supply section.

Abstract: There is provided a semiconductor switch apparatus that can handle a wide range of input voltages. The switch apparatus includes a main switch that is provided between a first terminal and a second terminal, and a switch controller that, to turn on the main switch, supplies the same gate-source voltage to the main switch irrespective of a direction of a current flowing through the main switch. To turn on the main switch, the switch controller supplies the gate-source voltage that is determined based on at least one of a voltage of the first terminal and a voltage of the second terminal to a gate of the main switch.

Abstract: To perform a forcible disconnection when voltage outside a reference range is applied to a terminal, provided is a switching apparatus comprising a main switch provided between a first terminal and a second terminal; a voltage detection section that detects whether voltage of the second terminal is within a reference range; and a control section that controls the main switch according to a control signal received from a control terminal and turns OFF the main switch when the voltage of the second terminal is outside the reference range. The voltage detection section includes a detection switch that disconnects the second terminal and the control section from each other when the voltage of the second terminal is within the reference range and connects the second terminal and the control section to each other when the voltage of the second terminal is outside the reference range.

Abstract: It is an objective to provide a semiconductor device with low leak current. The semiconductor device includes a plurality of ground side electrodes and a plurality of signal side electrodes arranged on a semiconductor substrate in an alternating manner; a plurality of control electrodes arranged respectively between each pair of a ground side electrode and a signal side electrode; a ground side electrode connecting section that connects the ground side electrodes to each other; a signal side electrode connecting section that connects the signal side electrodes to each other; and ground side lead wiring and signal side lead wiring that extend respectively from a region near one end and a region near another end of an arranged electrode section, in which the ground side electrodes and the signal side electrodes are arranged in an arrangement direction, away from the arranged electrode group in the arrangement direction.

Abstract: It is an objective to provide a semiconductor device with low leak current. The semiconductor device includes a plurality of ground side electrodes and a plurality of signal side electrodes arranged on a semiconductor substrate in an alternating manner; a plurality of control electrodes arranged respectively between each pair of a ground side electrode and a signal side electrode; a ground side electrode connecting section that connects the ground side electrodes to each other; a signal side electrode connecting section that connects the signal side electrodes to each other; and ground side lead wiring and signal side lead wiring that extend respectively from a region near one end and a region near another end of an arranged electrode section, in which the ground side electrodes and the signal side electrodes are arranged in an arrangement direction, away from the arranged electrode group in the arrangement direction.

Abstract: To perform a forcible disconnection when voltage outside a reference range is applied to a terminal, provided is a switching apparatus comprising a main switch provided between a first terminal and a second terminal; a voltage detection section that detects whether voltage of the second terminal is within a reference range; and a control section that controls the main switch according to a control signal received from a control terminal and turns OFF the main switch when the voltage of the second terminal is outside the reference range. The voltage detection section includes a detection switch that disconnects the second terminal and the control section from each other when the voltage of the second terminal is within the reference range and connects the second terminal and the control section to each other when the voltage of the second terminal is outside the reference range.

Abstract: A carrier transfer layer of compound semiconductor material is disposed on or over a support substrate, and a gate electrode of conductive material is disposed on or over the carrier transfer layer at a partial region thereof. A cap layer of non-doped compound semiconductor material is disposed on or over the carrier transfer layer at both sides of the gate electrode. The thickness of the cap layer is 100 nm or thicker. two current electrodes are formed in ohmic contact with the carrier transfer layer. An enhancement mode MESFET is provided whose gain and output power are suppressed from being lowered.

Abstract: A semiconductor device comprises a GaAs substrate 10; a buffer layer 12 formed on the GaAs substrate 10 and having a wider band gap than that of InGaP; a channel layer 14 formed on the buffer layer 12 and formed of an InGaP; a gate electrode 34 for controlling current of the channel layer 14. InGaP has a high carrier mobility and large .GAMMA.-L energy difference. Accordingly, the channel layer is formed of InGaP, whereby the semiconductor device which is operable at high speed and high voltage can be obtained.

Abstract: A field-effect transistor including a channel layer, a source electrode, a drain electrode, a high-resistance layer provided on the channel layer between the source electrode and the drain electrode and a gate electrode provided in an opening formed in the high-resistance layer, wherein the high-resistance layer is defined by a first side-wall facing the source electrode and a second side-wall facing the drain electrode, such that the first side-wall is separated from the source electrode.

Abstract: A method of fabricating a compound semiconductor device includes a step of removing a semiconductor layer by an etching process to expose an upper major surface of an underlying semiconductor layer, followed by a growth of another semiconductor layer of the p-type on the surface thus exposed, wherein the exposed surface is cleaned by a flushing of a gaseous metal organic compound containing a group V element for removing impurities therefrom and further doping the exposed surface to the p-type.

Abstract: A HEMT type semiconductor device includes a semiconductor substrate, a buffer semiconductor layer formed on the substrate, a first semiconductor well layer formed on the buffer layer and serving as a first conductivity type channel layer, a second semiconductor well layer formed on the first well layer and serving as a second conductivity type opposite the first conductivity, a channel layer and a potential barrier layer formed on the second well layer and forming a potential barrier for carriers. The substrate is made of GaAs or InP, and the layers are successively and epitaxially grown on the substrate. A two dimensional hole gas and a two dimensional electron gas are confined in the first well layer and in the second well layer, respectively.

Abstract: A semiconductor device includes an InP substrate, an intrinsic InGaAs channel layer formed on the InP substrate and lattice matched to the InP substrate, a doped GaAsSb carrier supply layer formed on the intrinsic InGaAs channel layer and lattice matched to the InP substrate, a gate electrode formed on the doped GaAsSb carrier supply layer, and a source electrode and a drain electrode which are respectively formed on the doped GaAsSb carrier supply layer and located on both sides of the gate electrode.

Abstract: A semiconductor device having a selectively doped heterostructure comprises a substrate, a channel layer, a carrier supplying layer, and electrodes provided on the carrier supplying layer. The channel layer and the carrier supplying layer form a heterojunction interface at a boundary between the channel layer and the carrier supplying layer with a two-dimensional electron gas formed in the channel layer along the heterojunction interface. The carrier supplying layer and the channel layer have respective compositions determined such that the .GAMMA. valley of the conduction band of the carrier supplying layer has an energetical level higher than a corresponding energetical level of the .GAMMA.

Abstract: A method for fabricating a compound semiconductor device having a semi-insulating layer of a group III-V compound semiconductor material that contains arsenic as a group V element. The method includes a step of growing the semi-insulating layer from a source gas of the group V element that contains both arsine and an organic compound of arsenic, wherein arsine and the organic compound of arsenic are used simultaneously with a mixing ratio to achieve a desired high resistivity in the semi-insulating layer.

Abstract: A semiconductor device includes an InP substrate, an intrinsic InGaAs channel layer formed on the InP substrate and lattice matched to the InP substrate, a doped GaAsSb carrier supply layer formed on the intrinsic InGaAs channel layer and lattice matched to the InP substrate, a gate electrode formed on the doped GaAsSb carrier supply layer, and a source electrode and a drain electrode which are respectively formed on the doped GaAsSb carrier supply layer and located on both sides of the gate electrode.

Abstract: A high electron mobility transistor comprises a semiinsulating substrate, an undoped channel layer formed on the semiinsulating substrate and made of undoped gallium arsenide (GaAs), a doped carrier supplying layer formed on the undoped channel layer and made of a II-VI family compound semiconductor having an electron affinity smaller than that of the undoped gallium arsenide and having an energy gap greater than that of the undoped gallium arsenide, and source, drain and gate electrodes formed on the doped carrier supplying layer.