Abstract: An apparatus sequentially acquires, from a plurality of reference imaging devices for imaging a silhouette imaged with a base imaging device from viewpoints different from a viewpoint of the base imaging device, silhouette existing position information based on the reference imaging devices, and transforms the silhouette existing position information into a common coordinate system, where the silhouette existing position information indicates an existing position of the silhouette. The apparatus detects a silhouette absence range in which the silhouette does not exist, based on a result of comparison of the silhouette existing position information acquired this time and the silhouette existing position information acquired last time, and searches a range in which the silhouette exists, based on the silhouette absence range.

Abstract: An apparatus sequentially acquires, from a plurality of reference imaging devices for imaging a silhouette imaged with a base imaging device from viewpoints different from a viewpoint of the base imaging device, silhouette existing position information based on the reference imaging devices, and transforms the silhouette existing position information into a common coordinate system, where the silhouette existing position information indicates an existing position of the silhouette. The apparatus detects a silhouette absence range in which the silhouette does not exist, based on a result of comparison of the silhouette existing position information acquired this time and the silhouette existing position information acquired last time, and searches a range in which the silhouette exists, based on the silhouette absence range.

Abstract: A processor controls a reconfigurable circuit capable of dynamically reconfiguring a circuit which achieves a task of a computer, the processor executes a process having determining, when reconfiguring each of circuits which achieve a plurality of tasks in the reconfigurable circuit, assigned times of time sharing of the plurality of tasks or priority processing ranks of the plurality of tasks based on costs needed in the reconfigurable circuit for respective circuits which achieve the plurality of tasks.

Abstract: A calculation device includes a programmable logic device including a plurality of circuit arrangement areas each to which power supply voltage allowed to be independently controlled is supplied and a calculation circuit coupled to the programmable logic device. The calculation circuit arranges a main circuit that executes specific processing in a first circuit arrangement area included in the plurality of circuit arrangement areas, acquires a second circuit arrangement area in which a sub circuit that executes the specific processing is allowed to be arranged, included in the plurality of circuit arrangement areas and in which the main circuit is not arranged, arranges the sub circuit in the second circuit arrangement area, and causes one of the main circuit and the sub circuit to execute the specific processing.

Abstract: A processor controls a reconfigurable circuit capable of dynamically reconfiguring a circuit which achieves a task of a computer, the processor executes a process having determining, when reconfiguring each of circuits which achieve a plurality of tasks in the reconfigurable circuit, assigned times of time sharing of the plurality of tasks or priority processing ranks of the plurality of tasks based on costs needed in the reconfigurable circuit for respective circuits which achieve the plurality of tasks.

Abstract: A calculation device includes: a programmable logic device including a plurality of circuit arrangement areas each to which power supply voltage allowed to be independently controlled is supplied; and a calculation circuit coupled to the programmable logic device, wherein the calculation circuit: arranges a main circuit that executes specific processing in a first circuit arrangement area included in the plurality of circuit arrangement areas; acquires a second circuit arrangement area in which a sub circuit that executes the specific processing is allowed to be arranged, included in the plurality of circuit arrangement areas and in which the main circuit is not arranged; arranges the sub circuit in the second circuit arrangement area; and causes one of the main circuit and the sub circuit to execute the specific processing.

Abstract: An image processing apparatus includes: a memory; and a processor coupled to the memory and configured to: detect, based on a reduced image of a target frame and a reduced image of a reference frame, a first motion vector of a target block divided from the target frame, set a search range including a pixel row in the target frame and parallel to the pixel row corresponding to a first pixel component that is specified by the first motion vector and substantially perpendicular to an edge direction of a block in the reference frame, calculate, for each of second pixel components corresponding to the first pixel component in the search range, an evaluation value representing a difference of a pixel value between the first pixel component and the second pixel component, and correct the first motion vector based on the evaluation value of each of the second pixel components.

Abstract: An operation processing device for executing a plurality of operations for aligned data by one vector instruction includes a first mask storage unit and a second mask storage unit. The first mask storage unit stores first mask data to designate each of the plurality of operations a true or false operation, and the second mask storage unit stores second mask data to designate a number to be true continuously, in the plurality of operations.

Abstract: A memory controller includes: a first generating unit that generates a read-address to read a data element sequence having a plurality of data elements from a bank of a memory; a second generating unit that generates a position signal indicating a position of a data element to be selected from the data element sequence, and an order signal indicating a storing order for storing the data element to be selected into a register; and a selector unit that selects, according to the position signal, the data element to be selected from the data element sequence read out from each of the plurality of the banks, and stores the selected data element in the storing order indicated by the order signal into the register, wherein the data element stored in the register is processed in the storing order by a vector processor.

Abstract: A memory controller includes: a first generating unit that generates a read-address to read a data element sequence having a plurality of data elements from a bank of a memory; a second generating unit that generates a position signal indicating a position of a data element to be selected from the data element sequence, and an order signal indicating a storing order for storing the data element to be selected into a register; and a selector unit that selects, according to the position signal, the data element to be selected from the data element sequence read out from each of the plurality of the banks, and stores the selected data element in the storing order indicated by the order signal into the register, wherein the data element stored in the register is processed in the storing order by a vector processor.

Abstract: A computer is made to execute the procedures of separating a hardware side from a software side within a reference source, and generating a merge model comprising a firmware interface for the software side to call the hardware side and comprising a hardware interface enabling an access to a mathematical function or a variable on the hardware side in response to a call from the firmware interface; and generating a system-on-chip (SoC) model comprising a CPU model for implementing a firmware interface with the software side, a hardware model for implementing the hardware side and a hardware interface connecting the CPU model to the hardware model.