Patents by Inventor Masahiko Yamauchi

Masahiko Yamauchi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12135082
    Abstract: An object of the present invention is to provide a vehicle parking lock system that realizes a parking lock with a positive user perception, and enables energy and cost reductions without complex control and with a simple configuration. The object is achieved by a selectable clutch configured to be switchable between four operating modes and provided to one of an input shaft, an output shaft, and an intermediate shaft of a transmission. The operating mode of the selectable clutch is controlled based on detection signals of a plurality of sensors to prevent an unintended movement of the vehicle when the vehicle is stationary.
    Type: Grant
    Filed: January 24, 2024
    Date of Patent: November 5, 2024
    Assignee: TSUBAKIMOTO CHAIN CO.
    Inventor: Masahiko Yamauchi
  • Patent number: 12127821
    Abstract: A measurement device includes a pressure acquisition unit configured to acquire pressure information representing pressure in a pressing cuff, a cuff pressure control unit configured to control, based on the pressure information, the pressure in the pressing cuff during each of a pressurizing step of pressurizing the pressing cuff, a pressurized state maintaining step of maintaining the pressing cuff in a pressurized state after end of the pressurizing step, and a depressurizing step of depressurizing the pressing cuff after end of the pressurized state maintaining step, a blood pressure calculation unit configured to calculate a blood pressure of a user based on the pressure information, and an electrocardiographic measurement unit configured to measure an electrocardiogram of the user during the pressurized state maintaining step.
    Type: Grant
    Filed: February 16, 2021
    Date of Patent: October 29, 2024
    Assignee: OMRON HEALTHCARE CO., LTD.
    Inventors: Toru Deno, Takahiro Hamaguchi, Masahiko Yumoto, Takanobu Yamauchi, Yasushi Matsuoka
  • Publication number: 20240344568
    Abstract: A plurality of rollers are disposed between an inner race and an outer race that are coaxial and relatively rotatable. The inner race and outer race are configured to engage with each other via part or all of the plurality of rollers that are held in a circumferential direction between roller support parts and pocket parts, the roller support parts being formed on one of an outer circumferential surface of the inner race and an inner circumferential surface of the outer race, and the pocket parts being formed on the other. A torque limiting member that applies a radial load on the rollers to press the rollers against the roller support parts is provided coaxially with the inner race and the outer race. The torque limiting member is flat and annular in an axial direction and resiliently deformable in a radial direction.
    Type: Application
    Filed: March 6, 2024
    Publication date: October 17, 2024
    Applicant: TSUBAKIMOTO CHAIN CO.
    Inventors: Masahiko Yamauchi, Yuji Kurematsu
  • Publication number: 20240314255
    Abstract: A color processing system includes one or plural processors configured to: acquire toner information indicating whether or not both a first condition, in which a special color toner to be added to a base color toner is a fluorescent toner, and a second condition, which is related to a printing order of the base color toner and the special color toner with respect to a recording medium on which an image is formed, are satisfied; and generate a color gamut, which is composed of the base color toner and the special color toner, by using a vertex of an outline of the color gamut corresponding to the toner information.
    Type: Application
    Filed: August 22, 2023
    Publication date: September 19, 2024
    Applicant: FUJIFILM Business Innovation Corp.
    Inventors: Mami YOKOHASHI, Kaoru YAMAUCHI, Toshihiro IWAFUCHI, Masahiko KUBO
  • Publication number: 20240288069
    Abstract: An object of the present invention is to provide a vehicle parking lock system that realizes a parking lock with a positive user perception, and enables energy and cost reductions without complex control and with a simple configuration. The object is achieved by a selectable clutch configured to be switchable between four operating modes and provided to one of an input shaft, an output shaft, and an intermediate shaft of a transmission. The operating mode of the selectable clutch is controlled based on detection signals of a plurality of sensors to prevent an unintended movement of the vehicle when the vehicle is stationary.
    Type: Application
    Filed: January 24, 2024
    Publication date: August 29, 2024
    Applicant: TSUBAKIMOTO CHAIN CO.
    Inventor: Masahiko Yamauchi
  • Patent number: 8892962
    Abstract: A failure detection method including: detecting, by a virtual computer, occurrence of the failure in a virtual function of an I/O device; acquiring, a virtual device name corresponding to the virtual function in which the failure has occurred; referring, to device information retaining a virtual device name of the I/O device assigned to the virtual computer and VF specific information on the I/O device, thereby acquiring the VF specific information based on the acquired virtual device name; transmitting, the acquired VF specific information to the host; referring, by the host, to I/O correspondence information retaining a slot number of a slot in which the I/O device is mounted, and VF specific information, thereby acquiring the slot number corresponding to the VF specific information received from the virtual computer; and identifying, the acquired slot number as the slot number of the I/O device on which the failure has occurred.
    Type: Grant
    Filed: September 27, 2012
    Date of Patent: November 18, 2014
    Assignee: Hitachi, Ltd.
    Inventors: Miho Iwanaga, Masahiko Yamauchi, Daisuke Nakayama
  • Publication number: 20130151908
    Abstract: A failure detection method including: detecting, by a virtual computer, occurrence of the failure in a virtual function of an I/O device; acquiring, a virtual device name corresponding to the virtual function in which the failure has occurred; referring, to device information retaining a virtual device name of the I/O device assigned to the virtual computer and VF specific information on the I/O device, thereby acquiring the VF specific information based on the acquired virtual device name; transmitting, the acquired VF specific information to the host; referring, by the host, to I/O correspondence information retaining a slot number of a slot in which the I/O device is mounted, and VF specific information, thereby acquiring the slot number corresponding to the VF specific information received from the virtual computer; and identifying, the acquired slot number as the slot number of the I/O device on which the failure has occurred.
    Type: Application
    Filed: September 27, 2012
    Publication date: June 13, 2013
    Inventors: Miho IWANAGA, Masahiko YAMAUCHI, Daisuke NAKAYAMA
  • Patent number: 7080227
    Abstract: An information processing apparatus for allowing a memory to be added thereto while being powered. The apparatus comprises a processor, a first main memory initially connected, and a connecting switch. The switch connects the processor, the first main memory, and a second main memory to be added. Main memory management information in the first main memory includes the size of memory resources connected to the processor. A storage region in the connecting switch retains information about whether or not the processor is connected to each of the memories. The setup allows the apparatus to use the added memory without having to be restarted.
    Type: Grant
    Filed: February 5, 2002
    Date of Patent: July 18, 2006
    Assignee: Hitachi, Ltd.
    Inventors: Hideki Murayama, Kazuo Horikawa, Hiroshi Yashiro, Masahiko Yamauchi, Yasuhiro Ishii, Daisuke Sasaki
  • Patent number: 7062627
    Abstract: An information processing apparatus for allowing a memory to be added thereto while being powered. The apparatus comprises a processor, a first main memory initially connected, and a connecting switch. The switch connects the processor, the first main memory, and a second main memory to be added. Main memory management information in the first main memory includes the size of memory resources connected to the processor. A storage region in the connecting switch retains information about whether or not the processor is connected to each of the memories. The setup allows the apparatus to use the added memory without having to be restarted.
    Type: Grant
    Filed: August 19, 2003
    Date of Patent: June 13, 2006
    Assignee: Hitachi, Ltd.
    Inventors: Hideki Murayama, Kazuo Horikawa, Hiroshi Yashiro, Masahiko Yamauchi, Yasuhiro Ishii, Daisuke Sasaki
  • Publication number: 20040054865
    Abstract: An information processing apparatus for allowing a memory to be added thereto while being powered. The apparatus comprises a processor, a first main memory initially connected, and a connecting switch. The switch connects the processor, the first main memory, and a second main memory to be added. Main memory management information in the first main memory includes the size of memory resources connected to the processor. A storage region in the connecting switch retains information about whether or not the processor is connected to each of the memories. The setup allows the apparatus to use the added memory without having to be restarted.
    Type: Application
    Filed: August 19, 2003
    Publication date: March 18, 2004
    Applicant: Hitachi, Limited
    Inventors: Hideki Murayama, Kazuo Horikawa, Hiroshi Yashiro, Masahiko Yamauchi, Yasuhiro Ishii, Daisuke Sasaki
  • Patent number: 6684312
    Abstract: An information processing apparatus for allowing a memory to be added thereto while being powered. The apparatus comprises a processor, a first main memory initially connected, and a connecting switch. The switch connects the processor, the first main memory, and a second main memory to be added. Main memory management information in the first main memory includes the size of memory resources connected to the processor. A storage region in the connecting switch retains information about whether or not the processor is connected to each of the memories. The setup allows the apparatus to use the added memory without having to be restarted.
    Type: Grant
    Filed: January 8, 1999
    Date of Patent: January 27, 2004
    Assignee: Hitachi, Ltd.
    Inventors: Hideki Murayama, Kazuo Horikawa, Hiroshi Yashiro, Masahiko Yamauchi, Yasuhiro Ishii, Daisuke Sasaki
  • Publication number: 20020073292
    Abstract: An information processing apparatus for allowing a memory to be added thereto while being powered. The apparatus comprises a processor, a first main memory initially connected, and a connecting switch. The switch connects the processor, the first main memory, and a second main memory to be added. Main memory management information in the first main memory includes the size of memory resources connected to the processor. A storage region in the connecting switch retains information about whether or not the processor is connected to each of the memories. The setup allows the apparatus to use the added memory without having to be restarted.
    Type: Application
    Filed: February 5, 2002
    Publication date: June 13, 2002
    Applicant: Hitachi, Limited
    Inventors: Hideki Murayama, Kazuo Horikawa, Hiroshi Yashiro, Masahiko Yamauchi, Yasuhiro Ishii, Daisuke Sasaki
  • Publication number: 20020029325
    Abstract: An information processing apparatus for allowing a memory to be added thereto while being powered. The apparatus comprises a processor, a first main memory initially connected, and a connecting switch. The switch connects the processor, the first main memory, and a second main memory to be added. Main memory management information in the first main memory includes the size of memory resources connected to the processor. A storage region in the connecting switch retains information about whether or not the processor is connected to each of the memories. The setup allows the apparatus to use the added memory without having to be restarted.
    Type: Application
    Filed: January 8, 1999
    Publication date: March 7, 2002
    Inventors: HIDEKI MURAYAMA, KAZUO HORIKAWA, HIROSHI YASHIRO, MASAHIKO YAMAUCHI, YASUHIRO ISHII, DAISUKE SASAKI
  • Patent number: 6318140
    Abstract: A laminated ring is manufactured by severing a cylindrical drum, which comprises a sheet of maraging steel with welded opposite ends, into a plurality of rings of predetermined width, rolling the rings to a predetermined target circumferential length, correcting circumferential lengths of the rings, aging and nitriding the rings, and laminating the rings into a laminated ring for transmitting power in a continuously variable transmission. A load applied to a circumferential edge of each of the rolled rings and a load applied to another circumferential edge thereof are measured while supporting an inner circumferential surface of the ring and applying a tensile load in a direction to expand the ring. The difference between circumferential lengths of the circumferential edges of the ring is detected based on the difference between the loads applied to the circumferential edges when the difference between the loads is maximum.
    Type: Grant
    Filed: September 27, 2000
    Date of Patent: November 20, 2001
    Assignee: Honda Giken Kogyo Kabushiki Kaisha
    Inventors: Hiroaki Yamagishi, Tomotsugu Takahashi, Masahiko Yamauchi
  • Patent number: 5867656
    Abstract: In a computer system in which nodes are connected to each other via a network, transmission and reception buffers of sender and receiver processes are prepared as resident areas in a main storage. A node of a receiver side notifies, prior to initiation of a communication, a physical address of a data reception area of the node to a node on a sender side. In the node on the sender side, the reported physical address is added to transmission data to transfer a resultant item. On the receiver side, reception data is written in a location of the main storage at the physical address. In the receiver node, the double buffering is employed to prevent an overwriting operation of another node onto the data reception area. The respective nodes achieve partial synchronization with adjacent nodes in chain, thereby automatically establishing synchronization between all nodes.
    Type: Grant
    Filed: December 3, 1996
    Date of Patent: February 2, 1999
    Assignee: Hitachi, Ltd.
    Inventors: Masaaki Iwasaki, Hiroyuki Chiba, Naoki Utsunomiya, Kouji Sonoda, Satoshi Yoshizawa, Masahiko Yamauchi
  • Patent number: 5659777
    Abstract: In a computer system in which nodes are connected to each other via a network, transmission and reception buffers of sender and receiver processes are prepared as resident areas in a main storage. A node of a receiver side notifies, prior to initiation of a communication, a physical address of a data reception area of the node to a node on a sender side. In the node on the sender side, the reported physical address is added to transmission data to transfer a resultant item. On the receiver side, reception data is written in a location of the main storage at the physical address. In the receiver node, the double buffering is employed to prevent an overwriting operation of another node onto the data reception area. The respective nodes achieve partial synchronization with adjacent nodes in chain, thereby automatically establishing synchronization between all nodes.
    Type: Grant
    Filed: September 23, 1993
    Date of Patent: August 19, 1997
    Assignee: Hitachi, Ltd.
    Inventors: Masaaki Iwasaki, Hiroyuki Chiba, Naoki Utsunomiya, Kouji Sonoda, Satoshi Yoshizawa, Masahiko Yamauchi
  • Patent number: 5649102
    Abstract: A distributed shared memory management system for a distributed shared memory computer system having a plurality of computers interconnected by a network, each computer having an independent address space and logically sharing data physically distributed to a storage of each computer. Each computer running a program for reading/changing the shared data includes a coherence control designation command for designating to enter a mutual exclusion state in which two or more computers cannot change the logically single shared data, a coherence control release command for designating a release of the mutual exclusion state, and a coherence control execution command for reflecting the contents of the shared data changed between the coherence control designation command and the coherence control release command, upon the logically single shared data in another computer.
    Type: Grant
    Filed: November 25, 1994
    Date of Patent: July 15, 1997
    Assignee: Hitachi, Ltd.
    Inventors: Masahiko Yamauchi, Satoshi Yoshizawa, Hideki Murayama, Takehisa Hayashi, Akira Kito, Hiroshi Yashiro, Tsutomu Goto, Kimitoshi Yamada, Toru Horimoto