Patents by Inventor Masahiko Yamauchi
Masahiko Yamauchi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 8892962Abstract: A failure detection method including: detecting, by a virtual computer, occurrence of the failure in a virtual function of an I/O device; acquiring, a virtual device name corresponding to the virtual function in which the failure has occurred; referring, to device information retaining a virtual device name of the I/O device assigned to the virtual computer and VF specific information on the I/O device, thereby acquiring the VF specific information based on the acquired virtual device name; transmitting, the acquired VF specific information to the host; referring, by the host, to I/O correspondence information retaining a slot number of a slot in which the I/O device is mounted, and VF specific information, thereby acquiring the slot number corresponding to the VF specific information received from the virtual computer; and identifying, the acquired slot number as the slot number of the I/O device on which the failure has occurred.Type: GrantFiled: September 27, 2012Date of Patent: November 18, 2014Assignee: Hitachi, Ltd.Inventors: Miho Iwanaga, Masahiko Yamauchi, Daisuke Nakayama
-
Publication number: 20130151908Abstract: A failure detection method including: detecting, by a virtual computer, occurrence of the failure in a virtual function of an I/O device; acquiring, a virtual device name corresponding to the virtual function in which the failure has occurred; referring, to device information retaining a virtual device name of the I/O device assigned to the virtual computer and VF specific information on the I/O device, thereby acquiring the VF specific information based on the acquired virtual device name; transmitting, the acquired VF specific information to the host; referring, by the host, to I/O correspondence information retaining a slot number of a slot in which the I/O device is mounted, and VF specific information, thereby acquiring the slot number corresponding to the VF specific information received from the virtual computer; and identifying, the acquired slot number as the slot number of the I/O device on which the failure has occurred.Type: ApplicationFiled: September 27, 2012Publication date: June 13, 2013Inventors: Miho IWANAGA, Masahiko YAMAUCHI, Daisuke NAKAYAMA
-
Patent number: 7080227Abstract: An information processing apparatus for allowing a memory to be added thereto while being powered. The apparatus comprises a processor, a first main memory initially connected, and a connecting switch. The switch connects the processor, the first main memory, and a second main memory to be added. Main memory management information in the first main memory includes the size of memory resources connected to the processor. A storage region in the connecting switch retains information about whether or not the processor is connected to each of the memories. The setup allows the apparatus to use the added memory without having to be restarted.Type: GrantFiled: February 5, 2002Date of Patent: July 18, 2006Assignee: Hitachi, Ltd.Inventors: Hideki Murayama, Kazuo Horikawa, Hiroshi Yashiro, Masahiko Yamauchi, Yasuhiro Ishii, Daisuke Sasaki
-
Patent number: 7062627Abstract: An information processing apparatus for allowing a memory to be added thereto while being powered. The apparatus comprises a processor, a first main memory initially connected, and a connecting switch. The switch connects the processor, the first main memory, and a second main memory to be added. Main memory management information in the first main memory includes the size of memory resources connected to the processor. A storage region in the connecting switch retains information about whether or not the processor is connected to each of the memories. The setup allows the apparatus to use the added memory without having to be restarted.Type: GrantFiled: August 19, 2003Date of Patent: June 13, 2006Assignee: Hitachi, Ltd.Inventors: Hideki Murayama, Kazuo Horikawa, Hiroshi Yashiro, Masahiko Yamauchi, Yasuhiro Ishii, Daisuke Sasaki
-
Publication number: 20040054865Abstract: An information processing apparatus for allowing a memory to be added thereto while being powered. The apparatus comprises a processor, a first main memory initially connected, and a connecting switch. The switch connects the processor, the first main memory, and a second main memory to be added. Main memory management information in the first main memory includes the size of memory resources connected to the processor. A storage region in the connecting switch retains information about whether or not the processor is connected to each of the memories. The setup allows the apparatus to use the added memory without having to be restarted.Type: ApplicationFiled: August 19, 2003Publication date: March 18, 2004Applicant: Hitachi, LimitedInventors: Hideki Murayama, Kazuo Horikawa, Hiroshi Yashiro, Masahiko Yamauchi, Yasuhiro Ishii, Daisuke Sasaki
-
Patent number: 6684312Abstract: An information processing apparatus for allowing a memory to be added thereto while being powered. The apparatus comprises a processor, a first main memory initially connected, and a connecting switch. The switch connects the processor, the first main memory, and a second main memory to be added. Main memory management information in the first main memory includes the size of memory resources connected to the processor. A storage region in the connecting switch retains information about whether or not the processor is connected to each of the memories. The setup allows the apparatus to use the added memory without having to be restarted.Type: GrantFiled: January 8, 1999Date of Patent: January 27, 2004Assignee: Hitachi, Ltd.Inventors: Hideki Murayama, Kazuo Horikawa, Hiroshi Yashiro, Masahiko Yamauchi, Yasuhiro Ishii, Daisuke Sasaki
-
Publication number: 20020073292Abstract: An information processing apparatus for allowing a memory to be added thereto while being powered. The apparatus comprises a processor, a first main memory initially connected, and a connecting switch. The switch connects the processor, the first main memory, and a second main memory to be added. Main memory management information in the first main memory includes the size of memory resources connected to the processor. A storage region in the connecting switch retains information about whether or not the processor is connected to each of the memories. The setup allows the apparatus to use the added memory without having to be restarted.Type: ApplicationFiled: February 5, 2002Publication date: June 13, 2002Applicant: Hitachi, LimitedInventors: Hideki Murayama, Kazuo Horikawa, Hiroshi Yashiro, Masahiko Yamauchi, Yasuhiro Ishii, Daisuke Sasaki
-
Publication number: 20020029325Abstract: An information processing apparatus for allowing a memory to be added thereto while being powered. The apparatus comprises a processor, a first main memory initially connected, and a connecting switch. The switch connects the processor, the first main memory, and a second main memory to be added. Main memory management information in the first main memory includes the size of memory resources connected to the processor. A storage region in the connecting switch retains information about whether or not the processor is connected to each of the memories. The setup allows the apparatus to use the added memory without having to be restarted.Type: ApplicationFiled: January 8, 1999Publication date: March 7, 2002Inventors: HIDEKI MURAYAMA, KAZUO HORIKAWA, HIROSHI YASHIRO, MASAHIKO YAMAUCHI, YASUHIRO ISHII, DAISUKE SASAKI
-
Patent number: 6318140Abstract: A laminated ring is manufactured by severing a cylindrical drum, which comprises a sheet of maraging steel with welded opposite ends, into a plurality of rings of predetermined width, rolling the rings to a predetermined target circumferential length, correcting circumferential lengths of the rings, aging and nitriding the rings, and laminating the rings into a laminated ring for transmitting power in a continuously variable transmission. A load applied to a circumferential edge of each of the rolled rings and a load applied to another circumferential edge thereof are measured while supporting an inner circumferential surface of the ring and applying a tensile load in a direction to expand the ring. The difference between circumferential lengths of the circumferential edges of the ring is detected based on the difference between the loads applied to the circumferential edges when the difference between the loads is maximum.Type: GrantFiled: September 27, 2000Date of Patent: November 20, 2001Assignee: Honda Giken Kogyo Kabushiki KaishaInventors: Hiroaki Yamagishi, Tomotsugu Takahashi, Masahiko Yamauchi
-
Patent number: 5867656Abstract: In a computer system in which nodes are connected to each other via a network, transmission and reception buffers of sender and receiver processes are prepared as resident areas in a main storage. A node of a receiver side notifies, prior to initiation of a communication, a physical address of a data reception area of the node to a node on a sender side. In the node on the sender side, the reported physical address is added to transmission data to transfer a resultant item. On the receiver side, reception data is written in a location of the main storage at the physical address. In the receiver node, the double buffering is employed to prevent an overwriting operation of another node onto the data reception area. The respective nodes achieve partial synchronization with adjacent nodes in chain, thereby automatically establishing synchronization between all nodes.Type: GrantFiled: December 3, 1996Date of Patent: February 2, 1999Assignee: Hitachi, Ltd.Inventors: Masaaki Iwasaki, Hiroyuki Chiba, Naoki Utsunomiya, Kouji Sonoda, Satoshi Yoshizawa, Masahiko Yamauchi
-
Patent number: 5659777Abstract: In a computer system in which nodes are connected to each other via a network, transmission and reception buffers of sender and receiver processes are prepared as resident areas in a main storage. A node of a receiver side notifies, prior to initiation of a communication, a physical address of a data reception area of the node to a node on a sender side. In the node on the sender side, the reported physical address is added to transmission data to transfer a resultant item. On the receiver side, reception data is written in a location of the main storage at the physical address. In the receiver node, the double buffering is employed to prevent an overwriting operation of another node onto the data reception area. The respective nodes achieve partial synchronization with adjacent nodes in chain, thereby automatically establishing synchronization between all nodes.Type: GrantFiled: September 23, 1993Date of Patent: August 19, 1997Assignee: Hitachi, Ltd.Inventors: Masaaki Iwasaki, Hiroyuki Chiba, Naoki Utsunomiya, Kouji Sonoda, Satoshi Yoshizawa, Masahiko Yamauchi
-
Patent number: 5649102Abstract: A distributed shared memory management system for a distributed shared memory computer system having a plurality of computers interconnected by a network, each computer having an independent address space and logically sharing data physically distributed to a storage of each computer. Each computer running a program for reading/changing the shared data includes a coherence control designation command for designating to enter a mutual exclusion state in which two or more computers cannot change the logically single shared data, a coherence control release command for designating a release of the mutual exclusion state, and a coherence control execution command for reflecting the contents of the shared data changed between the coherence control designation command and the coherence control release command, upon the logically single shared data in another computer.Type: GrantFiled: November 25, 1994Date of Patent: July 15, 1997Assignee: Hitachi, Ltd.Inventors: Masahiko Yamauchi, Satoshi Yoshizawa, Hideki Murayama, Takehisa Hayashi, Akira Kito, Hiroshi Yashiro, Tsutomu Goto, Kimitoshi Yamada, Toru Horimoto