Abstract: A diffusion time when forming an isolation region is shortened without deteriorating strength against wafer cracks. A plurality of circular holes 4a and 4b are respectively provided side by side on both surfaces of the wafer discontinuously and intermittently along a scribe line SL between semiconductor devices which are adjacent to each other, and isolation diffusion layers 5a and 5b in a single conductivity type (here, P-type) used for element isolation are respectively formed around the plurality of circular holes 4a and 4b so as to reach a center portion in a depth direction from the both surfaces of the wafer and to be at least partially overlapped with each other between adjacent holes and between upper and lower bottom surfaces.

Abstract: A semiconductor apparatus according to the present invention has a P-type well and an N-type well, with impurity concentration of a high impurity concentration region deeper than the P-type well and the N-type well being from 1×1017 cm?3 to 1×1019 cm?3, and the apparatus comprises a first channel separating section for separating elements, and a depth of the first channel separating section is equal to or deeper than the high impurity concentration region.

Abstract: The invention provides a method for producing a semiconductor device that can reduce the number of mask steps. In a CMOS production process, gate electrodes are formed in regions for forming an NMOS and a PMOS at the same time with a common mask pattern, and after the gate electrodes have been formed, a well, and source and drain regions are formed by impurity ion implantations with a common mask pattern in each region of the NMOS and the PMOS, using the gate electrode as a mask, whereby the number of mask steps is reduced.

Abstract: The invention provides a method for producing a semiconductor device that can reduce the number of mask steps. In a CMOS production process, gate electrodes are formed in regions for forming an NMOS and a PMOS at the same time with a common mask pattern, and after the gate electrodes have been formed, a well, and source and drain regions are formed by impurity ion implantations with a common mask pattern in each region of the NMOS and the PMOS, using the gate electrode as a mask, whereby the number of mask steps is reduced.

Abstract: A method of manufacturing a semiconductor memory device includes the steps of providing a gate insulating film on an active region, depositing a first conductive film on the gate insulating film, processing the first conductive film, the gate insulating film, and the active region to provide an opening of which the bottom is located below the interface between the active region and the gate insulating film and then providing a gate electrode between the openings, depositing a first insulating film which covers the side and bottom surface of the opening, depositing a second insulating film over the first insulating film, shaping the first and second insulating films into a side wall spacer shape by etching to provide charge retention sections beside the gate electrode and providing diffusion areas at opposite sides of the gate electrode beneath the charge retention sections in the active region.

Abstract: A method of manufacturing a semiconductor memory device includes the steps of providing a gate insulating film on an active region, depositing a first conductive film on the gate insulating film, processing the first conductive film, the gate insulating film, and the active region to provide an opening of which the bottom is located below the interface between the active region and the gate insulating film and then providing a gate electrode between the openings, depositing a first insulating film which covers the side and bottom surface of the opening, depositing a second insulating film over the first insulating film, shaping the first and second insulating films into a side wall spacer shape by etching to provide charge retention sections beside the gate electrode and providing diffusion areas at opposite sides of the gate electrode beneath the charge retention sections in the active region.

Abstract: A semiconductor memory device including a substrate on which a memory cell array portion and a peripheral circuit portion for the memory cell array portion are provided, the surface of the memory cell array portion being higher than the surface of the peripheral circuit portion. A glass layer is formed on the peripheral circuit portion with the glass layer having a predetermined thickness for offsetting the difference in height between the surface of the memory cell array portion and that of the peripheral circuit portion, so as to provide a substantially even surface over the memory cell array portion and the peripheral circuit portion. A metal wiring for the memory cell array portion and the peripheral circuit portion is formed in a predetermined pattern on the substantially even surface.

Abstract: A dynamic random access memory device for storing 2-bit information, including a memory cell having two access transistors and one capacitor, wherein one of the access transistors is composed of a thin film transistor and disposed above the other access transistor which is formed in a substrate; and the capacitor is sandwiched by the two access transistors.

Abstract: The present invention provides a process for fabricating a semiconductor device including the steps of: depositing a CVD film by a bias ECRCVD process on a wiring layer having an intended contact region in which a wiring line are made wider than in other regions; coating planarly the CVD film with a resist film; etching the resist film back so as to expose a protuberance of the CVD film formed above the inteded contact region; and etching the protuberance and the CVD film thereunder to open a contact hole down to the intended contact region of the wiring layer.