Abstract: A semiconductor device includes: an n-channel MIS transistor and a p-channel MIS transistor. An n-channel MIS transistor includes: a first gate insulating film having an amorphous layer or an epitaxial layer formed on a p-type semiconductor region between a first source/drain regions; and a first gate electrode having a stack structure formed with a first metal layer and a first compound layer. The first metal layer is formed on the first gate insulating film and made of a first metal having a work function of 4.3 eV or smaller, and the first compound layer is formed on the first metal layer and contains a compound of a second metal and a IV-group semiconductor. The second metal is different from the first metal. A p-channel MIS transistor includes a second gate electrode having a second compound layer containing a compound of the same composition as the first compound layer.

Abstract: A semiconductor device includes n- and p-type semiconductor regions separately formed on a substrate, an interlayer insulator formed on the substrate and having first and second trenches formed to reach the n- and p-type regions. There are further included first and second gate insulators formed inside of the first and second trenches, a first metal layer formed inside of the first trench via the first gate insulator, a second metal layer formed in a thickness of 1 monolayer or more and 1.5 nm or less inside of the second trench via the second gate insulator, a third metal layer formed on the second metal layer and containing at least one of a simple substance, a nitride, a carbide and an oxide of at least one metal element of alkaline earth metal elements and group III elements, first and second source/drain regions formed on the n- and p-type regions.

Abstract: A semiconductor device includes: an n-channel MIS transistor and a p-channel MIS transistor. An n-channel MIS transistor includes: a first gate insulating film having an amorphous layer or an epitaxial layer formed on a p-type semiconductor region between a first source/drain regions; and a first gate electrode having a stack structure formed with a first metal layer and a first compound layer. The first metal layer is formed on the first gate insulating film and made of a first metal having a work function of 4.3 eV or smaller, and the first compound layer is formed on the first metal layer and contains a compound of a second metal and a IV-group semiconductor. The second metal is different from the first metal. A p-channel MIS transistor includes a second gate electrode having a second compound layer containing a compound of the same composition as the first compound layer.

Abstract: A semiconductor device includes: an n-channel MIS transistor and a p-channel MIS transistor. An n-channel MIS transistor includes: a first gate insulating film having an amorphous layer or an epitaxial layer formed on a p-type semiconductor region between a first source/drain regions; and a first gate electrode having a stack structure formed with a first metal layer and a first compound layer. The first metal layer is formed on the first gate insulating film and made of a first metal having a work function of 4.3 eV or smaller, and the first compound layer is formed on the first metal layer and contains a compound of a second metal and a IV-group semiconductor. The second metal is different from the first metal. A p-channel MIS transistor includes a second gate electrode having a second compound layer containing a compound of the same composition as the first compound layer.

Abstract: A semiconductor device includes: an n-channel MIS transistor and a p-channel MIS transistor. An n-channel MIS transistor includes: a first gate insulating film having an amorphous layer or an epitaxial layer formed on a p-type semiconductor region between a first source/drain regions; and a first gate electrode having a stack structure formed with a first metal layer and a first compound layer. The first metal layer is formed on the first gate insulating film and made of a first metal having a work function of 4.3 eV or smaller, and the first compound layer is formed on the first metal layer and contains a compound of a second metal and a IV-group semiconductor. The second metal is different from the first metal. A p-channel MIS transistor includes a second gate electrode having a second compound layer containing a compound of the same composition as the first compound layer.

Abstract: A semiconductor device includes: an n-channel MIS transistor and a p-channel MIS transistor. An n-channel MIS transistor includes: a first gate insulating film having an amorphous layer or an epitaxial layer formed on a p-type semiconductor region between a first source/drain regions; and a first gate electrode having a stack structure formed with a first metal layer and a first compound layer. The first metal layer is formed on the first gate insulating film and made of a first metal having a work function of 4.3 eV or smaller, and the first compound layer is formed on the first metal layer and contains a compound of a second metal and a IV-group semiconductor. The second metal is different from the first metal. A p-channel MIS transistor includes a second gate electrode having a second compound layer containing a compound of the same composition as the first compound layer.

Abstract: A semiconductor device includes n- and p-type semiconductor regions separately formed on a substrate, an interlayer insulator formed on the substrate and having first and second trenches formed to reach the n- and p-type regions. There are further included first and second gate insulators formed inside of the first and second trenches, a first metal layer formed inside of the first trench via the first gate insulator, a second metal layer formed in a thickness of 1 monolayer or more and 1.5 nm or less inside of the second trench via the second gate insulator, a third metal layer formed on the second metal layer and containing at least one of a simple substance, a nitride, a carbide and an oxide of at least one metal element of alkaline earth metal elements and group III elements, first and second source/drain regions formed on the n- and p-type regions.

Abstract: According to an aspect of the invention, a semiconductor device comprises: a N-channel MIS transistor comprising; a p-type semiconductor layer; a first gate insulation layer formed on the p-type semiconductor layer; a first gate electrode formed on the first gate insulation layer; and a first source-drain region formed in the p-type semiconductor layer where the first gate electrode is sandwiched along a direction of gate length. The first gate electrode comprises a crystal phase including a cubic crystal of NiSi2 which has a lattice constant of 5.39 angstroms to 5.40 angstroms.

Abstract: According to an aspect of the invention, a semiconductor device comprises: a N-channel MIS transistor comprising; a p-type semiconductor layer; a first gate insulation layer formed on the p-type semiconductor layer; a first gate electrode formed on the first gate insulation layer; and a first source-drain region formed in the p-type semiconductor layer where the first gate electrode is sandwiched along a direction of gate length. The first gate electrode comprises a crystal phase including a cubic crystal of NiSi2 which has a lattice constant of 5.39 angstroms to 5.40 angstroms.

Abstract: A method and device to accurately obtain very small quantity of wear of the order of nanometers of a protective film on the surface of a sliding member. A quantity of wear on the surface of a measurement sample including a base and a coating layer is measured by making a spectrum of the surface elements in a reference sample using a surface-element analysis device which analyzes elements on the surface of a substance from an energy spectrum of charged particles obtained by applying excited ionization radiation on the reference sample equivalent to the measurement and by measuring charged particles generated from the surface of the substance. A step of obtaining signal intensity ratios of plural elements from the spectrum is repeated a plurality of times while the surface of the reference sample is being etched and calibration curves which indicate a distribution of the signal intensity ratios of the plural elements in the reference sample are made.

Abstract: A deconvolution analysis apparatus includes a sputtering rate calibrating unit that calibrates a depth profile resulting from a depth analysis on a sample to be estimated by using a sputtering surface analysis, according to a depth change of a sputtering rate in an initial sputtering; and a deconvolution analysis unit that performs a deconvolution analysis on the depth profile whose depth axis is extended, so as to make a depth change of a depth resolution in the initial sputtering apparently constant.

Abstract: A semiconductor device includes: an n-channel MIS transistor and a p-channel MIS transistor. An n-channel MIS transistor includes: a first gate insulating film having an amorphous layer or an epitaxial layer formed on a p-type semiconductor region between a first source/drain regions; and a first gate electrode having a stack structure formed with a first metal layer and a first compound layer. The first metal layer is formed on the first gate insulating film and made of a first metal having a work function of 4.3 eV or smaller, and the first compound layer is formed on the first metal layer and contains a compound of a second metal and a IV-group semiconductor. The second metal is different from the first metal. A p-channel MIS transistor includes a second gate electrode having a second compound layer containing a compound of the same composition as the first compound layer.

Abstract: According to an aspect of the invention, a semiconductor device comprises: a N-channel MIS transistor comprising; a p-type semiconductor layer; a first gate insulation layer formed on the p-type semiconductor layer; a first gate electrode formed on the first gate insulation layer; and a first source-drain region formed in the p-type semiconductor layer where the first gate electrode is sandwiched along a direction of gate length. The first gate electrode comprises a crystal phase including a cubic crystal of NiSi2 which has a lattice constant of 5.39 angstroms to 5.40 angstroms.

Abstract: It is made possible to control the effective work function of the gate electrode so that the transistor can have an optimum operating threshold voltage. A semiconductor device includes: a semiconductor substrate; a gate insulating film provided on the semiconductor substrate; a gate electrode provided on the gate insulating film; source/drain regions provided in the semiconductor substrate on both sides of the gate electrode; and a layer which is provided at an interface between the gate electrode and the gate insulating film, and contains an element having an electronegativity different from those of elements constituting the gate electrode and the gate insulating film.

Abstract: A deconvolution analysis apparatus includes a sputtering rate calibrating unit that calibrates a depth profile resulting from a depth analysis on a sample to be estimated by using a sputtering surface analysis, according to a depth change of a sputtering rate in an initial sputtering; and a deconvolution analysis unit that performs a deconvolution analysis on the depth profile whose depth axis is extended, so as to make a depth change of a depth resolution in the initial sputtering apparently constant.

Abstract: An object of the present invention is to provide means for accurately obtaining very small quantity of wear of the order of nanometers of a protective film on the surface of a sliding member. In a method of measuring a quantity of wear on the surface of a measurement sample comprising a base and a coating layer, a spectrum of the surface of a reference sample is made, using a surface-element analysis device which analyzes elements on the surface of a substance from an energy spectrum of charged particles which is obtained by applying excited ionization radiation on the reference sample equivalent to the measurement one and by measuring charged particles generated from the surface of the substance. A step of obtaining signal intensity ratios of plural elements from the spectrum is repeated a plurality of times while the surface of the reference sample is being etched and calibration curves which indicates a distribution of the signal intensity ratios of the plural elements in the reference sample are made.

Abstract: An object of the present invention is to provide means for accurately obtaining very small quantity of wear of the order of nanometers of a protective film on the surface of a sliding member. In a method of measuring a quantity of wear on the surface of a measurement sample comprising a base and a coating layer, a spectrum of the surface of a reference sample is made, using a surface-element analysis device which analyzes elements on the surface of a substance from an energy spectrum of charged particles which is obtained by applying excited ionization radiation on the reference sample equivalent to the measurement one and by measuring charged particles generated from the surface of the substance. A step of obtaining signal intensity ratios of plural elements from the spectrum is repeated a plurality of times while the surface of the reference sample is being etched and calibration curves which indicates a distribution of the signal intensity ratios of the plural elements in the reference sample are made.

Abstract: The invention provides a method for concentrating impurity contained in a semiconductor crystal sample 11 by irradiating repeatedly a specified position of the semiconductor crystal sample 11 with a laser beam having a specified intensity by means of a laser oscillator 13. Then the invention provides a method for analyzing impurity contained in the impurity concentrated area of the semiconductor crystal sample 11 in high sensitivity by means of a specified physical analyzing means. According to demand, a method of the invention concentrates impurity by means of a laser beam after forming an insulating film such as an oxide film and the like transparent to the laser beam on the surface of the semiconductor crystal sample. At the same time, the invention provides a concentrator and an analyzer to be used for these concentrating method and analyzing method.

Abstract: An impurity diffusion layer shallow in diffusion depth and high in activity is formed in a semiconductor device. In the semiconductor device, clusters of icosahedron structure each composed of boron atoms are formed in the silicon crystal of the impurity layer of the semiconductor device so as to function as acceptors. Further, after the clusters of icosahedron structure each composed of 12 boron atoms have been formed by implanting boron ions at high concentration, the device is processed at temperature lower than 700.degree. C. to prevent the boron from being decreased due to combination with silicon. Since an impurity layer shallow in diffusion from the substrate surface and high in activity can be formed and further the clusters of icosahedron structure each composed of 12 boron atoms can be utilized as acceptors, it is possible to realize a high doping even in the manufacturing process for the devices not suitable for high temperature annealing.

Abstract: An impurity diffusion layer shallow in diffusion depth and high in activity is formed in a semiconductor device. In the semiconductor device, clusters of icosahedron structure each composed of boron atoms are formed in the silicon crystal of the impurity layer of the semiconductor device so as to function as acceptors. Further, after the clusters of icosahedron structure each composed of 12 boron atoms have been formed by implanting boron ions at high concentration, the device is processed at temperature lower than 700.degree. C. to prevent the boron from being decreased due to combination with silicon. Since an impurity layer shallow in diffusion from the substrate surface and high in activity can be formed and further the clusters of icosahedron structure each composed of 12 boron atoms can be utilized as acceptors, it is possible to realize a high doping even in the manufacturing process for the devices not suitable for high temperature annealing.