Patents by Inventor Masahiro Aoyagi
Masahiro Aoyagi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11270968Abstract: The purpose of the present invention is to provide an electronic circuit connection method and an electronic circuit capable of improving the reliability of electrical connection. A connection method for an electronic circuit 100 includes: a process of forming a first metal bumps 30 and a second metal bump 40, each of which has a cone shape; and a process of joining a first electrode pad 12 and a third electrode pad 22 by the first metal bump 30 and joining a second electrode pad 13 and a fourth electrode pad 23 by the second metal bump 40, wherein at least one region of between a first region 11a and a second region 11b in a first connection surface 11 and between a third region 21a and a fourth region 21b in a second connection surface 21 has a step 11c, and the first metal bump 30 and the second metal bump 40 have different heights so as to correct a height H1 of the step 11c.Type: GrantFiled: May 30, 2019Date of Patent: March 8, 2022Assignee: NATIONAL INSTITUTE OF ADVANCED INDUSTRIAL SCIENCE AND TECHNOLOGYInventors: Masaru Hashino, Ying Ying Lim, Hiroshi Nakagawa, Masahiro Aoyagi, Katsuya Kikuchi
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Publication number: 20210249374Abstract: The purpose of the present invention is to provide an electronic circuit connection method and an electronic circuit capable of improving the reliability of electrical connection. A connection method for an electronic circuit 100 includes: a process of forming a first metal bumps 30 and a second metal bump 40, each of which has a cone shape; and a process of joining a first electrode pad 12 and a third electrode pad 22 by the first metal bump 30 and joining a second electrode pad 13 and a fourth electrode pad 23 by the second metal bump 40, wherein at least one region of between a first region 11a and a second region 11b in a first connection surface 11 and between a third region 21a and a fourth region 21b in a second connection surface 21 has a step 11c, and the first metal bump 30 and the second metal bump 40 have different heights so as to correct a height H1 of the step 11c.Type: ApplicationFiled: May 30, 2019Publication date: August 12, 2021Applicant: NATIONAL INSTITUTE OF ADVANCED INDUSTRIAL SCIENCE AND TECHNOLOGYInventors: Masaru HASHINO, Ying Ying LIM, Hiroshi NAKAGAWA, Masahiro AOYAGI, Katsuya KIKUCHI
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Patent number: 9984956Abstract: Provided are a through electrode including an organic side-wall insulating film, capable of eliminating a barrier layer and achieving satisfactory mechanical reliability and electrical reliability and a manufacturing method thereof, and a semiconductor device and a manufacturing method thereof. According to one aspect of the present invention, a through electrode disposed in a semiconductor substrate is provided, including: a copper layer in the semiconductor substrate; and a side-wall insulating film that is disposed between the copper layer and the semiconductor substrate so as to be in contact with the copper layer and the semiconductor substrate, the side-wall insulating film being represented by the following chemical formula (1).Type: GrantFiled: October 30, 2015Date of Patent: May 29, 2018Assignee: National Institute of Advanced Industrial Science and TechnologyInventors: Masahiro Aoyagi, Tung Thanh Bui, Naoya Watanabe, Fumiki Kato, Katsuya Kikuchi
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Patent number: 9818645Abstract: Embodiments provided are a through electrode that can be manufactured by a method not including the step of removing a side-wall insulating film formed at the bottom part of the through hole and so having improved electrical characteristics and mechanical reliability and a manufacturing method thereof as well as a semiconductor device and a manufacturing method thereof. A through electrode is disposed in a semiconductor substrate, and includes: a conductive layer; a side-wall insulating film that is disposed between the conductive layer and the semiconductor substrate, the side-wall insulating film being represented by the following chemical formula (1), and a tubular semiconductor layer disposed between the conductive layer and the semiconductor substrate, the semiconductor layer including a same material as the material of the semiconductor substrate.Type: GrantFiled: August 30, 2016Date of Patent: November 14, 2017Assignee: NATIONAL INSTITUTE OF ADVANCED INDUSTRIAL SCIENCE AND TECHNOLOGYInventors: Masahiro Aoyagi, Tung Thanh Bui, Naoya Watanabe, Katsuya Kikuchi, Wei Feng
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Publication number: 20170200644Abstract: Embodiments provided are a through electrode that can be manufactured by a method not including the step of removing a side-wall insulating film formed at the bottom part of the through hole and so having improved electrical characteristics and mechanical reliability and a manufacturing method thereof as well as a semiconductor device and a manufacturing method thereof. A through electrode is disposed in a semiconductor substrate, and includes: a conductive layer; a side-wall insulating film that is disposed between the conductive layer and the semiconductor substrate, the side-wall insulating film being represented by the following chemical formula (1), and a tubular semiconductor layer disposed between the conductive layer and the semiconductor substrate, the semiconductor layer including a same material as the material of the semiconductor substrate.Type: ApplicationFiled: August 30, 2016Publication date: July 13, 2017Inventors: Masahiro AOYAGI, Tung Thanh BUI, Naoya WATANABE, Katsuya KIKUCHI, Wei FENG
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Patent number: 9627347Abstract: A method of manufacturing a semiconductor device according to the present invention comprises: a bump forming step of forming a bump electrode 100 on a semiconductor chip 1, the bump electrode 100 protruding in a substantially conical shape; a pad forming step of forming a pad electrode 200 on a substrate 10, the pad electrode 200 having a recess 210 with inner lateral surfaces thereof defining a substantially pyramidal shape or a prism shape; a pressing step of pressing the bump electrode 100 and the pad electrode 200 in a direction which brings them closer to each other, with the bump electrode 100 being inserted in the recess 210 so that the central axis of the bump electrode 100 and the central axis of the recess 210 coincide with each other; and an ultrasonic joining step of joining the bump electrode 100 and the pad electrode 200 by vibrating at least one of the bump electrode 100 and the pad electrode 200 using ultrasonic waves.Type: GrantFiled: August 29, 2013Date of Patent: April 18, 2017Assignee: National Institute of Advanced Industrial Science and TechnologyInventors: Masahiro Aoyagi, Thanh Tung Bui, Motohiro Suzuki, Naoya Watanabe, Fumiki Kato, Lai Na Ma, Shunsuke Nemoto
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Publication number: 20160322282Abstract: Provided are a through electrode including an organic side-wall insulating film, capable of eliminating a barrier layer and achieving satisfactory mechanical reliability and electrical reliability and a manufacturing method thereof, and a semiconductor device and a manufacturing method thereof. According to one aspect of the present invention, a through electrode disposed in a semiconductor substrate is provided, including: a copper layer in the semiconductor substrate; and a side-wall insulating film that is disposed between the copper layer and the semiconductor substrate so as to be in contact with the copper layer and the semiconductor substrate, the side-wall insulating film being represented by the following chemical formula (1).Type: ApplicationFiled: October 30, 2015Publication date: November 3, 2016Inventors: Masahiro AOYAGI, Tung Thanh BUI, Naoya WATANABE, Fumiki KATO, Katsuya KIKUCHI
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Patent number: 9345145Abstract: An electroless gold plating solution with which one or more openings formed in a resist overlying a substrate can be filled in a short time, the openings having a width on the order of micrometer, in particular, 100 ?m or smaller, in terms of the width of the exposed substrate area, and having a height of 3 ?m or larger. The electroless gold plating solution contains a deposition accelerator for deposition in fine areas, and a microfine pattern of 100 ?m or finer is formed therefrom.Type: GrantFiled: March 10, 2010Date of Patent: May 17, 2016Assignee: Kanto Kagaku Kabushiki KaishaInventors: Ryota Iwai, Tomoaki Tokuhisa, Masaru Kato, Tokihiko Yokoshima, Masahiro Aoyagi, Yasuhiro Yamaji, Katsuya Kikuchi, Hiroshi Nakagawa
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Patent number: 9134346Abstract: A method of making a contact probe including a step of making a first printed wiring board having a signal electrode and a ground electrode used as a contact part of the contact probe with respect to a measuring object, in which the signal electrode and ground electrode are formed of a metal wiring pattern, and making a second printed wiring board with a coaxial line structure having a shield electrode which encloses a signal line and the surroundings of the signal line through an insulating layer. The signal electrode of the first printed wiring board and the signal line of the second printed wiring board are electrically connected together, and the ground electrode of the first printed wiring board and the shield electrode of the second printed wiring board are electrically connected together.Type: GrantFiled: June 24, 2011Date of Patent: September 15, 2015Assignees: NATIONAL INSTITUTE OF ADVANCED INDUSTRIAL SCIENCE AND TECHNOLOGY, KIYOTO MANUFACTURING CO.Inventors: Masahiro Aoyagi, Katsuya Kikuchi, Hiroshi Nakagawa, Yoshikuni Okada, Hiroyuki Fujita, Shouichi Imai, Shigeo Kiyota
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Publication number: 20150235984Abstract: A method of manufacturing a semiconductor device according to the present invention comprises: a bump forming step of forming a bump electrode 100 on a semiconductor chip 1, the bump electrode 100 protruding in a substantially conical shape; a pad forming step of forming a pad electrode 200 on a substrate 10, the pad electrode 200 having a recess 210 with inner lateral surfaces thereof defining a substantially pyramidal shape or a prism shape; a pressing step of pressing the bump electrode 100 and the pad electrode 200 in a direction which brings them closer to each other, with the bump electrode 100 being inserted in the recess 210 so that the central axis of the bump electrode 100 and the central axis of the recess 210 coincide with each other; and an ultrasonic joining step of joining the bump electrode 100 and the pad electrode 200 by vibrating at least one of the bump electrode 100 and the pad electrode 200 using ultrasonic waves.Type: ApplicationFiled: August 29, 2013Publication date: August 20, 2015Applicant: National Institute of Advanced Industrial Science and TechnologyInventors: Masahiro Aoyagi, Thanh Tung Bui, Motohiro Suzuki, Naoya Watanabe, Fumiki Kato, Lai Na Ma, Shunsuke Nemoto
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Patent number: 8399979Abstract: An electrode connection structure of a semiconductor chip is provided to realize a highly reliable electrical connection with low stress without using a bump. A conductive member may be used for such an electrode connection structure. A semiconductor device is provided wherein semiconductor chips are arranged in layers without providing the semiconductor chips with a through via, and a method is provided for manufacturing such a semiconductor device. A part or all of the surface of a horizontal recess, which is formed in an adhesive layer arranged between a first electrode of a lower layer and a second electrode of an upper layer, is provided with a conductive member for connecting the first electrode and the second electrode.Type: GrantFiled: July 6, 2007Date of Patent: March 19, 2013Assignee: National Institute of Advanced Industrial Science and TechnologyInventors: Yasuhiro Yamaji, Tokihiko Yokoshima, Masahiro Aoyagi, Hiroshi Nakagawa, Katsuya Kikuchi
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Patent number: 8367468Abstract: An electrode connection structure of a semiconductor chip is provided to realize a highly reliable electrical connection with low stress without using a bump. A conductive member may be used for such an electrode connection structure. A semiconductor device is provided wherein semiconductor chips are arranged in layers without providing the semiconductor chips with a through via, and a method is provided for manufacturing such a semiconductor device. A part or all of the surface of a horizontal recess, which is formed in an adhesive layer arranged between a first electrode of a lower layer and a second electrode of an upper layer, is provided with a conductive member for connecting the first electrode and the second electrode.Type: GrantFiled: April 28, 2011Date of Patent: February 5, 2013Assignee: National Institute of Advanced Industrial Science and TechnologyInventors: Yasuhiro Yamaji, Tokihiko Yokoshima, Masahiro Aoyagi, Hiroshi Nakagawa, Katsuya Kikuchi
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Publication number: 20120119352Abstract: An electroless gold plating solution with which one or more openings formed in a resist overlying a substrate can be filled in a short time, the openings having a width on the order of micrometer, in particular, 100 ?m or smaller, in terms of the width of the exposed substrate area, and having a height of 3 ?m or larger. The electroless gold plating solution contains a deposition accelerator for deposition in fine areas, and a microfine pattern of 100 ?m or finer is formed therefrom.Type: ApplicationFiled: March 10, 2010Publication date: May 17, 2012Applicant: Kanto Kagaku Kabushiki KaishaInventors: Ryota Iwai, Tomoaki Tokuhisa, Masaru Kato, Tokihiro Yokoshima, Masahiro Aoyagi, Yasuhiro Yamaji, Katsuya Kikuchi, Hiroshi Nakagawa
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Publication number: 20120108008Abstract: An electrode connection structure of a semiconductor chip is provided to realize a highly reliable electrical connection with low stress without using a bump. A conductive member may be used for such an electrode connection structure. A semiconductor device is provided wherein semiconductor chips are arranged in layers without providing the semiconductor chips with a through via, and a method is provided for manufacturing such a semiconductor device. A part or all of the surface of a horizontal recess, which is formed in an adhesive layer arranged between a first electrode of a lower layer and a second electrode of an upper layer, is provided with a conductive member for connecting the first electrode and the second electrode.Type: ApplicationFiled: April 28, 2011Publication date: May 3, 2012Applicant: National Institute of Advanced Industrial Science and TechnologyInventors: Yasuhiro Yamaji, Tokihiko Yokoshima, Masahiro Aoyagi, Hiroshi Nakagawa, Katsuya Kikuchi
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Publication number: 20110247209Abstract: [Problem] To provide a contact probe which can easily be connected with a measurement apparatus electrically, can measure a high speed and high frequency signal with a fine pitch easily and correctly, and can easily cope with signal measurement for a plurality of channels, and a method of making the contact probe. [Means to Solve Problem] It includes a first printed wiring board 3 having a signal electrode 10a and a ground electrode 10b used as a contact part with respect to a measuring object, in which the signal electrode 10a and ground electrode 10b are formed of a metal wiring pattern on a substrate, and a second printed wiring board 2 with a coaxial line structure having shield electrodes 12, 17, 18 which enclose a signal line 15a and the surroundings of the signal line 15a through an insulating layer.Type: ApplicationFiled: June 24, 2011Publication date: October 13, 2011Applicants: NATIONAL INSTITUTE OF ADVANCED INDUSTRIAL SCIENCE AND TECHNOLOGY, KIYOTA MANUFACTURING CO., TSS CORPORATIONInventors: Masahiro Aoyagi, Katsuya Kikuchi, Hiroshi Nakagawa, Yoshikuni Okada, Hiroyuki Fujita, Shouichi Imai, Shigeo Kiyota
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Patent number: 7990165Abstract: To provide a contact probe which can easily be connected with a measurement apparatus electrically, can measure a high speed and high frequency signal with a fine pitch easily and correctly, and can easily cope with signal measurement for a plurality of channels, and a method of making the contact probe. It includes a first printed wiring board 3 having a signal electrode 10a and a ground electrode 10b used as a contact part with respect to a measuring object, in which the signal electrode 10a and ground electrode 10b are formed of a metal wiring pattern on a substrate, and a second printed wiring board 2 with a coaxial line structure having shield electrodes 12, 17, 18 which enclose a signal line 15a and the surroundings of the signal line 15a through an insulating layer.Type: GrantFiled: April 19, 2007Date of Patent: August 2, 2011Assignees: National Institute of Advanced Industrial Science and Technology, Kiyoto Manufacturing Co., TSS CorporationInventors: Masahiro Aoyagi, Katsuya Kikuchi, Hiroshi Nakagawa, Yoshikuni Okada, Hiroyuki Fujita, Shoichi Imai, Shigeo Kiyota
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Patent number: 7833835Abstract: An interposer having multi-layer fine wiring structure which comprises an insulating layer made of photosensitive polyimide which is photosensitive organic material and a wiring layer portion made of metal, such as copper, silver, gold, aluminum, palladium, indium, titanium, tantalum, and niobium, functions as wiring in an integrated circuit chip, wherein junctions between the integrated circuit chip and the interposer are formed by micron to submicron size fine connection metal pads or bumps which are formed on both the integrated circuit chip and the interposer.Type: GrantFiled: August 7, 2007Date of Patent: November 16, 2010Assignee: National Institute of Advanced Industrial Science and TechnologyInventors: Masahiro Aoyagi, Hiroshi Nakagawa, Kazuhiko Tokoro, Katsuya Kikuchi, Yoshikuni Okada
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Patent number: 7767574Abstract: The present invention provides a method of forming a micro metal bump, which is capable of stably and industrially forming a micro metal bump, by a gas deposition process, at a prescribed position of a metal part formed on one side surface of a substrate.Type: GrantFiled: March 30, 2007Date of Patent: August 3, 2010Assignees: Kabushiki Kaisha Mikuni Kogyo, National Institute of Advanced Industrial Science and TechnologyInventors: Yoshihiro Gomi, Masahiro Aoyagi, Hiroshi Nakagawa, Katsuya Kikuchi, Yoshikuni Okada, Hirotaka Oosato
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Publication number: 20100044870Abstract: An electrode connection structure of a semiconductor chip is provided to realize a highly reliable electrical connection with low stress without using a bump. A conductive member may be used for such an electrode connection structure. A semiconductor device is provided wherein semiconductor chips are arranged in layers without providing the semiconductor chips with a through via, and a method is provided for manufacturing such a semiconductor device. A part or all of the surface of a horizontal recess, which is formed in an adhesive layer arranged between a first electrode of a lower layer and a second electrode of an upper layer, is provided with a conductive member for connecting the first electrode and the second electrode.Type: ApplicationFiled: July 6, 2007Publication date: February 25, 2010Applicant: National Institute of Advanced Industrial Science and TechnologyInventors: Yasuhiro Yamaji, Tokihiko Yokoshima, Masahiro Aoyagi, Hiroshi Nakagawa, Katsuya Kikuchi
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Publication number: 20090224781Abstract: [Problem]To provide a contact probe which can easily be connected with a measurement apparatus electrically, can measure a high speed and high frequency signal with a fine pitch easily and correctly, and can easily cope with signal measurement for a plurality of channels, and a method of making the contact probe. [Means to Solve Problem] It includes a first printed wiring board 3 having a signal electrode 10a and a ground electrode 10b used as a contact part with respect to a measuring object, in which the signal electrode 10a and ground electrode 10b are formed of a metal wiring pattern on a substrate, and a second printed wiring board 2 with a coaxial line structure having shield electrodes 12, 17, 18 which enclose a signal line 15a and the surroundings of the signal line 15a through an insulating layer.Type: ApplicationFiled: April 19, 2007Publication date: September 10, 2009Applicants: SHINWA FRONTECH CORP., KIYOTA MANUFACTURING CO.Inventors: Masahiro Aoyagi, Katsuya Kikuchi, Hiroshi Nakagawa, Yoshikuni Okada, Hiroyuki Fujita, Shouichi Imai, Shigeo Kiyota