Patents by Inventor Masahiro Araki
Masahiro Araki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240079856Abstract: A method for fabricating a quality and manufacturable aperture for light emitting elements, such as vertical cavity surface emitting lasers (VCSELs), using epitaxial later overgrowth (ELO). A bar comprised of island-like III-nitride semiconductor layers is grown on a substrate using a growth restrict mask, and the island-like III-nitride semiconductor layers are fabricated into light-emitting resonating cavities across a smallest length of the bar. Apertures for the resonating cavities are also fabricated along the smallest length of the bar on wing regions of the epitaxial lateral overgrowth. Distributed Bragg reflectors (DBRs) are fabricated as mirrors for the resonant cavities on the bottom and top of the wing regions of the epitaxial lateral overgrowth.Type: ApplicationFiled: October 23, 2020Publication date: March 7, 2024Applicant: The Regents of the University of CaliforniaInventors: Gandrothula Srinlvas, Takeshi Kamikawa, Masahiro Araki
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Publication number: 20230140914Abstract: A method of manufacturing a semiconductor element includes: forming a first semiconductor layer (SL1) and a second semiconductor layer (SL2) larger in thickness than the first semiconductor layer (SL1) on a mask layer (ML) including a first opening portion (K1) and a second opening portion (K2); forming a first device layer (DL1) and a second device layer (DL2); and bonding the first device layer (DL1) and the second device layer (DL2) to a support substrate (SK).Type: ApplicationFiled: March 29, 2021Publication date: May 11, 2023Applicant: KYOCERA CorporationInventors: Katsuaki MASAKI, Masahiro ARAKI
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Publication number: 20230127257Abstract: An epitaxial lateral overgrowth (ELO) of a III-nitride layer is used to cover a growth restrict mask deposited on a substrate, wherein the III-nitride ELO layer is grown with a low V/III ratio of less than 500 resulting in high-speed lateral growth as compared to low-speed vertical growth. The III-nitride ELO layer contains a large amount of impurities, over 1 × 1018 cm-3, which result in the III-nitride ELO layer comprising a coloring layer. The coloring layer absorbs light from an active region due to the large amount of impurities. When a bar of device layers is removed from the substrate, at least a portion of the coloring layer is removed from the bar. The elimination of the coloring layer reduces absorption losses, which makes the device characteristics improve.Type: ApplicationFiled: April 19, 2021Publication date: April 27, 2023Applicant: The Regents of the University of CaliforniaInventors: Takeshi Kamikawa, Masahiro Araki, Srinivas Gandrothula
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Patent number: 11379072Abstract: A semiconductor device comprises a pulse signal output circuit providing a pulse signal for a transmission electrode of an electrode pair, a current converter converting a first current generated on the reception electrode to a second current, a current-controlled oscillator outputting an oscillation signal having a frequency depending on the second current, and a counter counting a number of oscillating times of the oscillation signal per a predetermined period; wherein the current converter comprises a first constant current source and output a combined current of the first constant current of the first constant current source and the first current as the second current in response to the pulse signal, so that the semiconductor device suppresses an increase circuit size.Type: GrantFiled: April 3, 2020Date of Patent: July 5, 2022Assignee: RENESAS ELECTRONICS CORPORATIONInventor: Masahiro Araki
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Patent number: 11360234Abstract: The present invention provides an electrode device, semiconductor device and a semiconductor system capable of accuracy detecting an object to be detected. According to one embodiment, the electrode device 11 is used for detecting the capacitance of the mutual capacitance system, and includes a reception electrode PR1, a transmission electrode PX1 arranged to face the reception electrode PR1, a transmission electrode PX2 arranged to face the reception electrode PR1 with the transmission electrode PX1 interposed therebetween, and a dielectric board 101 provided between the transmission electrode PX1 and the transmission electrode PX2 to fix the distance and the dielectric constant between the transmission electrode PX1 and the transmission electrode PX2.Type: GrantFiled: March 26, 2020Date of Patent: June 14, 2022Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Takuya Mizokami, Masahiro Araki
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Publication number: 20220181210Abstract: A method for removing devices from a substrate using a supporting plate. One or more bars comprised of semiconductor layers are formed on a substrate, and one or more device structures are formed on the bars. At least one supporting plate is bonded to the bars, and stress is applied to the supporting plate to remove the bars from the substrate. The supporting plate is used to divide the bars into one or more device units after the bars are removed from the substrate, wherein the device units are packaged and arranged into one or more modules. The supporting plate may also be used to make a cleavage facet for one or more of the device structures after the bars are removed from the substrate.Type: ApplicationFiled: March 12, 2020Publication date: June 9, 2022Applicant: The Regents of the University of CaliforniaInventors: Takeshi Kamikawa, Srinivas Gandrothula, Masahiro Araki
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Publication number: 20220165570Abstract: Epitaxial lateral overgrowth (ELO) III-nitride layers are grown on or above an opening area of a growth restrict mask deposited on a substrate, wherein the growth of the ELO III-nitride layers and/or a subsequent regrowth layer form one or more voids. III-nitride device layers are grown on or above the ELO III-nitride layers and/or regrowth layer. Stress is applied to a breaking point at the substrate, with the voids assisting the application of stress, so that a bar of devices comprised of the III-nitride device layers, the ELO III-nitride layers and the regrowth layer is removed from the substrate. The voids release stress from the growth restrict mask, which helps prevent cracks. Decomposition of the growth restrict mask is avoided to prevent compensation of p-type layers.Type: ApplicationFiled: March 13, 2020Publication date: May 26, 2022Applicant: The Regents of the University of CaliforniaInventors: Takeshi Kamikawa, Masahiro Araki, Srinivas Gandrothula
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Publication number: 20220123166Abstract: An epitaxial lateral overgrowth (ELO) layer is grown on an opening area of a substrate, wherein the ELO layer is higher than a surface 5 of a trench in the substrate. The trench is apt to form a symmetric shape of the ELO layer, which renders it suitable for flip-chip bonding The shape of the ELO layer has a depressed surface region at a back side of a bar formed by the ELO layer. A cleaving point is located higher than the bottom of the ELO layer, so that a force can be efficiently applied to 10 the cleaving point for removing the bar.Type: ApplicationFiled: January 16, 2020Publication date: April 21, 2022Applicant: The Regents of the University of CaliforniaInventors: Takeshi Kamikawa, Srinivas Gandrothula, Masahiro Araki
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Publication number: 20220064818Abstract: A method of manufacturing a semiconductor element according to the present disclosure includes a mask forming step of defining, on a first surface of a substrate, a front surface region not covered by a first deposition inhibiting mask as a first crystal growth region, an element forming step of forming a semiconductor layer over the first crystal growth region, a mask removing step of removing the mask, and an element separating step of separating the semiconductor layer.Type: ApplicationFiled: December 25, 2019Publication date: March 3, 2022Inventor: Masahiro ARAKI
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Publication number: 20200379600Abstract: A semiconductor device comprises a pulse signal output circuit providing a pulse signal for a transmission electrode of an electrode pair, a current converter converting a first current generated on the reception electrode to a second current, a current-controlled oscillator outputting an oscillation signal having a frequency depending on the second current, and a counter counting a number of oscillating times of the oscillation signal per a predetermined period; wherein the current converter comprises a first constant current source and output a combined current of the first constant current of the first constant current source and the first current as the second current in response to the pulse signal, so that the semiconductor device suppresses an increase circuit size.Type: ApplicationFiled: April 3, 2020Publication date: December 3, 2020Inventor: Masahiro ARAKI
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Publication number: 20200341165Abstract: The present invention provides an electrode device, semiconductor device and a semiconductor system capable of accuracy detecting an object to be detected. According to one embodiment, the electrode device 11 is used for detecting the capacitance of the mutual capacitance system, and includes a reception electrode PR1, a transmission electrode PX1 arranged to face the reception electrode PR1, a transmission electrode PX2 arranged to face the reception electrode PR1 with the transmission electrode PX1 interposed therebetween, and a dielectric board 101 provided between the transmission electrode PX1 and the transmission electrode PX2 to fix the distance and the dielectric constant between the transmission electrode PX1 and the transmission electrode PX2.Type: ApplicationFiled: March 26, 2020Publication date: October 29, 2020Inventors: Takuya MIZOKAMI, Masahiro ARAKI
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Patent number: 10615032Abstract: A semiconductor device manufacturing method according to the present disclosure includes: preparing a substrate having a surface layer at least made of semiconductor; forming a mask pattern having a plurality of openings on the surface layer using materials free of semiconductor vapor-phase growth; forming a brittle portion in each opening by a vapor-phase growth process; forming crystal growth-derived layer on the mask pattern by a vapor-phase growth process by growth of semiconductor crystals on a surface of the brittle portion ; and separating, at brittle portion, a crystal growth-derived layer from substrate.Type: GrantFiled: January 22, 2019Date of Patent: April 7, 2020Assignee: Kyocera CorporationInventor: Masahiro Araki
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Publication number: 20190237324Abstract: A semiconductor device manufacturing method according to the present disclosure includes: preparing a substrate having a surface layer at least made of semiconductor; forming a mask pattern having a plurality of openings on the surface layer using materials free of semiconductor vapor-phase growth; forming a brittle portion in each opening by a vapor-phase growth process; forming crystal growth-derived layer on the mask pattern by a vapor-phase growth process by growth of semiconductor crystals on a surface of the brittle portion ; and separating, at brittle portion, a crystal growth-derived layer from substrate.Type: ApplicationFiled: January 22, 2019Publication date: August 1, 2019Applicant: KYOCERA CorporationInventor: Masahiro ARAKI
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Patent number: 10082919Abstract: A semiconductor device containing a terminal, a power supply voltage dropping circuit that generates a constant voltage, a switch circuit to periodically apply a constant voltage to a terminal in response to a first clock, a current-controlled oscillator circuit, and a counter, and in which the power supply voltage dropping circuit supplies a first current to the switch circuit, the current-controlled oscillator circuit generates a second clock whose frequency changes in response to the value of the first current, and the counter counts the number of second clocks within the counting time.Type: GrantFiled: November 30, 2016Date of Patent: September 25, 2018Assignee: Renesas Electronics CorporationInventor: Masahiro Araki
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Publication number: 20170083132Abstract: A semiconductor device containing a terminal, a power supply voltage dropping circuit that generates a constant voltage, a switch circuit to periodically apply a constant voltage to a terminal in response to a first clock, a current-controlled oscillator circuit, and a counter, and in which the power supply voltage dropping circuit supplies a first current to the switch circuit, the current-controlled oscillator circuit generates a second clock whose frequency changes in response to the value of the first current, and the counter counts the number of second clocks within the counting time.Type: ApplicationFiled: November 30, 2016Publication date: March 23, 2017Inventor: Masahiro ARAKI
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Patent number: 9543947Abstract: A semiconductor device containing a terminal, a power supply voltage dropping circuit that generates a constant voltage, a switch circuit to periodically apply a constant voltage to a terminal in response to a first clock, a current-controlled oscillator circuit, and a counter, and in which the power supply voltage dropping circuit supplies a first current to the switch circuit, the current-controlled oscillator circuit generates a second clock whose frequency changes in response to the value of the first current, and the counter counts the number of second clocks within the counting time.Type: GrantFiled: May 27, 2014Date of Patent: January 10, 2017Assignee: Renesas Electronics CorporationInventor: Masahiro Araki
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Publication number: 20160110023Abstract: A semiconductor device includes a terminal to which a touch electrode may be coupled; a source voltage drop circuit generating a constant voltage; a phase shift circuit generating a phase shifted clock in response to a first clock and a phase control signal; and a switching circuit to which the constant voltage is supplied. The switching circuit generates drive pulses for applying the constant voltage to the terminal in response to the phase shifted clock. The phase shift circuit varies the phase of the drive pulses based on the phase control signal.Type: ApplicationFiled: December 21, 2015Publication date: April 21, 2016Inventor: Masahiro Araki
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Patent number: 9257976Abstract: A semiconductor device includes a terminal to which a touch electrode may be coupled; a source voltage drop circuit generating a constant voltage; a phase shift circuit generating a phase shifted clock in response to a first clock and a phase control signal; and a switching circuit to which the constant voltage is supplied. The switching circuit generates drive pulses for applying the constant voltage to the terminal in response to the phase shifted clock. The phase shift circuit varies the phase of the drive pulses based on the phase control signal.Type: GrantFiled: November 13, 2014Date of Patent: February 9, 2016Assignee: Renesas Electronics CorporationInventor: Masahiro Araki
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Publication number: 20150145578Abstract: The problem was that the noise superimposed on a touch electrode via the human body can incur erroneous touch determination by a touch sensor circuit. The invention provides a semiconductor device including a terminal to which a touch electrode may be coupled; a source voltage drop circuit generating a constant voltage; a phase shift circuit generating a phase shifted clock in response to a first clock and a phase control signal; and a switching circuit to which the constant voltage is supplied. The switching circuit generates drive pulses for applying the constant voltage to the terminal in response to the phase shifted clock. The phase shift circuit varies the phase of the drive pulses based on the phase control signal.Type: ApplicationFiled: November 13, 2014Publication date: May 28, 2015Inventor: Masahiro ARAKI
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Patent number: 8963165Abstract: A nitride semiconductor structure in which a first nitride semiconductor underlying layer is provided on a substrate having a recess portion and a projection portion provided between the recess portions at a surface thereof, the first nitride semiconductor underlying layer has at least 6 first oblique facet planes surrounding the projection portion on an outer side of the projection portion, and a second nitride semiconductor underlying layer buries the first oblique facet planes, a nitride semiconductor light emitting element, a nitride semiconductor transistor element, a method of manufacturing a nitride semiconductor structure, and a method of manufacturing a nitride semiconductor element are provided.Type: GrantFiled: December 21, 2011Date of Patent: February 24, 2015Assignee: Sharp Kabushiki KaishaInventors: Masahiro Araki, Shinya Yoshida, Haruhisa Takiguchi, Atsushi Ogawa, Takao Kinoshita, Tohru Murata, Takeshi Funaki, Masayuki Hoteida