Patents by Inventor Masahiro Chijiiwa

Masahiro Chijiiwa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7592655
    Abstract: A semiconductor image sensor includes: a semiconductor substrate having a number of pixels disposed in a matrix shape, the semiconductor substrate comprising a first region including a charge accumulation region of a photodiode and a floating diffusion and a second region including transistors, each having a gate electrode and source/drain regions; a first silicon oxide film formed above the semiconductor substrate, covering the surface of the charge accumulation region in the first region and formed as side wall spacers on side of the gate electrode walls of at lease some transistors in the second region; and a silicon nitride film formed above the first silicon oxide film, covering the source/drain regions in the second region and having an opening at least in an area above the charge accumulation region in the first region. The semiconductor image sensor is provided which has a high sensitivity and can supply an output with small noises.
    Type: Grant
    Filed: September 1, 2005
    Date of Patent: September 22, 2009
    Assignee: Fujitsu Microelectronics Limited
    Inventors: Narumi Ohkawa, Shigetoshi Takeda, Yukihiro Ishihara, Kazuki Hayashi, Nobuhisa Naori, Masahiro Chijiiwa
  • Publication number: 20060208289
    Abstract: A semiconductor image sensor includes: a semiconductor substrate having a number of pixels disposed in a matrix shape, the semiconductor substrate comprising a first region including a charge accumulation region of a photodiode and a floating diffusion and a second region including transistors, each having a gate electrode and source/drain regions; a first silicon oxide film formed above the semiconductor substrate, covering the surface of the charge accumulation region in the first region and formed as side wall spacers on side of the gate electrode walls of at lease some transistors in the second region; and a silicon nitride film formed above the first silicon oxide film, covering the source/drain regions in the second region and having an opening at least in an area above the charge accumulation region in the first region. The semiconductor image sensor is provided which has a high sensitivity and can supply an output with small noises.
    Type: Application
    Filed: September 1, 2005
    Publication date: September 21, 2006
    Applicant: FUJITSU LIMITED
    Inventors: Narumi Ohkawa, Shigetoshi Takeda, Yukihiro Ishihara, Kazuki Hayashi, Nobuhisa Naori, Masahiro Chijiiwa
  • Patent number: 7005690
    Abstract: The solid-state image sensor includes a pixel part 10, an analog circuit part 12, a digital circuit part 14 and an input/output circuit part 16. The digital circuit part 14 includes a first well 42c of a second conduction type formed in a second region of a semiconductor substrate 20 of a first conduction type surrounding a first region thereof; a first buried diffused layer 40c of the second conduction type buried in the first region: a second well 44b of the first conduction type formed near a surface of the semiconductor substrate 20 in the first region; and a first transistor 38e formed on the second well 44b.
    Type: Grant
    Filed: December 6, 2004
    Date of Patent: February 28, 2006
    Assignee: Fujitsu Limited
    Inventors: Masahiro Chijiiwa, Shigetoshi Takeda, Masaya Katayama
  • Publication number: 20060011956
    Abstract: The solid-state image sensor includes a pixel part 10, an analog circuit part 12, a digital circuit part 14 and an input/output circuit part 16. The digital circuit part 14 includes a first well 42c of a second conduction type formed in a second region of a semiconductor substrate 20 of a first conduction type surrounding a first region thereof; a first buried diffused layer 40c of the second conduction type buried in the first region: a second well 44b of the first conduction type formed near a surface of the semiconductor substrate 20 in the first region; and a first transistor 38e formed on the second well 44b.
    Type: Application
    Filed: December 6, 2004
    Publication date: January 19, 2006
    Applicant: FUJITSU LIMITED
    Inventors: Masahiro Chijiiwa, Shigetoshi Takeda, Masaya Katayama