Abstract: An information processing apparatus includes: a memory; and a processor coupled to the memory and configured to: perform an arithmetic operation using an arithmetic operation target; repeat the arithmetic operation by using a calculated arithmetic operation result; obtain a ratio of, in a first number of elements which are included in the arithmetic operation result, a second number of elements in an expressible range as a predetermined-bit fixed point; and perform the arithmetic operation by using the predetermined-bit fixed point based on the ratio.

Abstract: A computing system includes one or more processors configured to perform generation of a plurality of pieces of segment data by dividing first data, generate a plurality of pieces of extended data by performing an extension process on each of the plurality of pieces of segment data, each extended data having a size equal to a size of second data, generate first combination data by combining first extended data included in the plurality of pieces of extended data and the second data, perform transmission of the first combination data, in response to receiving data of a computation result calculated based on the first combination data, generate a first computation result related to the first extended data by dividing the data of the computation result, and generate a third computation result related to the first data by performing a reconstruction process based on the first computation result.

Abstract: An information processing apparatus includes: a memory; and a processor coupled to the memory and configured to: perform an arithmetic operation using an arithmetic operation target; repeat the arithmetic operation by using a calculated arithmetic operation result; obtain a ratio of, in a first number of elements which are included in the arithmetic operation result, a second number of elements in an expressible range as a predetermined-bit fixed point; and perform the arithmetic operation by using the predetermined-bit fixed point based on the ratio.

Abstract: A computing system includes one or more processors configured to perform generation of a plurality of pieces of segment data by dividing first data, generate a plurality of pieces of extended data by performing an extension process on each of the plurality of pieces of segment data, each extended data having a size equal to a size of second data, generate first combination data by combining first extended data included in the plurality of pieces of extended data and the second data, perform transmission of the first combination data, in response to receiving data of a computation result calculated based on the first combination data, generate a first computation result related to the first extended data by dividing the data of the computation result, and generate a third computation result related to the first data by performing a reconstruction process based on the first computation result.

Abstract: A compiler apparatus copies a branch instruction included in first code to produce a plurality of branch instructions. The compiler apparatus generates a control instruction to cause different threads running on a processor, which is able to execute a plurality of threads that share storage space for storing information to be used for branch prediction, to execute different ones of the plurality of branch instructions. The compiler apparatus generates second code including the plurality of branch instructions and the control instruction.

Abstract: An information processing apparatus that mounts a first and second system boards SB#0 and SB#1 includes a virtualization control unit that operates a virtual machine for virtualizing hardware resources. The SB#0 includes a memory that stores a command line, resource information, and management information. The SB#1 includes a memory that stores a command line and resource information. The command line is executed by the virtualization control unit. The resource information is data used by each system board from among data used when the virtualization control unit operates. The management information is data commonly shared by each system board and used by the virtualization control unit. A command line and resource information are used when the virtualization control unit operates and information on the hardware resources included in the corresponding SB. Each SB executes the command line and refers to the information stored in the memory in SBs.

Abstract: A compiler apparatus copies a branch instruction included in first code to produce a plurality of branch instructions. The compiler apparatus generates a control instruction to cause different threads running on a processor, which is able to execute a plurality of threads that share storage space for storing information to be used for branch prediction, to execute different ones of the plurality of branch instructions. The compiler apparatus generates second code including the plurality of branch instructions and the control instruction.

Abstract: A first computing device includes a data transmission processing unit transmitting data to be transferred to another computing device to a first storage area among the plurality of storage areas, and an interrupt generating unit generating an interrupt corresponding to transmission of data by the data transmission processing unit with respect to a transmission destination of the data together with identification information specifying the storage area, and a second computing device includes an interrupt processing unit specifying from which computing device the interrupt is requested based on the identification information received together with the interrupt when receiving the interrupt, and a data receiving unit reading out data from the first storage area corresponding to the computing device specified by the interrupt processing unit among the plurality of storage areas to efficiently communicate among computing devices in an information processing apparatus including a plurality of computing devices.

Abstract: A first computing device includes a data transmission processing unit transmitting data to be transferred to another computing device to a first storage area among the plurality of storage areas, and an interrupt generating unit generating an interrupt corresponding to transmission of data by the data transmission processing unit with respect to a transmission destination of the data together with identification information specifying the storage area, and a second computing device includes an interrupt processing unit specifying from which computing device the interrupt is requested based on the identification information received together with the interrupt when receiving the interrupt, and a data receiving unit reading out data from the first storage area corresponding to the computing device specified by the interrupt processing unit among the plurality of storage areas to efficiently communicate among computing devices in an information processing apparatus including a plurality of computing devices.

Abstract: An information processing apparatus that mounts a first and second system boards SB#0 and SB#1 includes a virtualization control unit that operates a virtual machine for virtualizing hardware resources. The SB#0 includes a memory that stores a command line, resource information, and management information. The SB#1 includes a memory that stores a command line and resource information. The command line is executed by the virtualization control unit. The resource information is data used by each system board from among data used when the virtualization control unit operates. The management information is data commonly shared by each system board and used by the virtualization control unit. A command line and resource information are used when the virtualization control unit operates and information on the hardware resources included in the corresponding SB. Each SB executes the command line and refers to the information stored in the memory in SBs.

Abstract: A program generating apparatus includes a second program generating unit to generate a second program including a memory image that reproduces data used to execute a subsection by a first arithmetic unit, subsection information including initial value information at the start position of the subsection, a program controlling portion to store the memory image in a second storing unit used by a second arithmetic unit, to set the second arithmetic unit to the same state as the first arithmetic unit at the start position of the subsection, and to cause the second arithmetic unit to execute the subsection of a first program, a monitor program including a function needed to execute the first program, and a monitor program initializing portion to make settings for causing the monitor program to provide a service requested when the second arithmetic unit executes the first program.

Abstract: Context information pertaining to the virtual address is obtained, and a storage location for storing the address translation information is determined based on the context information.

Abstract: Context information pertaining to the virtual address is obtained, and a storage location for storing the address translation information is determined based on the context information.

Abstract: In order to enable a plurality of access origins to effectively utilize a cache thereby to realize high-speed and stable processing, by measuring a frequency of access from the plurality of access origins, allocating a cache capacity based on the access frequency, and notifying an error, when it occurs, to an access origin having the allocation or to a predetermined access origin to process the error, there is provided a cache apparatus for enabling a plurality of access origins to make access to a cache memory. The cache apparatus comprises a unit for setting a cache capacity into which each access origin can charge data; a unit for charging data into an area within the set cache capacity in response to a request from each access origin based on the cache capacity; and a unit for reading data from the cache memory and notifying the data without depending on the set cache capacity when each access origin has made a reference request.