Patents by Inventor Masahiro Fujikawa

Masahiro Fujikawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11961765
    Abstract: The present invention relates to a method for manufacturing a semiconductor substrate, including: (a) preparing an epitaxial substrate having a nitride semiconductor layer formed on a first main surface of a growth substrate and preparing a first support substrate, forming a resin adhesive layer between the first main surface of the growth substrate and a first main surface of the first support substrate, and bonding the epitaxial substrate to the first support substrate; (b) thinning a second main surface of the growth substrate; (c) forming a first protective thin film layer on the thinned growth substrate; (d) forming a second protective thin film layer on the first support substrate; (e) removing the thinned growth substrate; (f) bonding a second support substrate onto the nitride semiconductor layer; and (g) removing the first support substrate and the resin adhesive layer.
    Type: Grant
    Filed: May 23, 2019
    Date of Patent: April 16, 2024
    Assignee: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Shuichi Hiza, Kunihiko Nishimura, Masahiro Fujikawa, Yuki Takiguchi, Eiji Yagyu
  • Patent number: 11854856
    Abstract: An object is to provide a technique capable of suppressing defectives in semiconductor elements. A manufacturing method of a semiconductor device includes a step of forming a laminated body in which an adhesive protective layer, an adhesive layer, a peeling layer, and a support substrate are disposed in this order on a first main surface of the semiconductor substrate, a step of removing the semiconductor substrate other than a portion where a plurality of circuit elements are formed, a step of bonding the portion where the circuit elements are formed to a transfer substrate, a step of removing the peeling layer, the support substrate and the adhesive layer, a step of removing the adhesive protective layer by chemical treatment, and a step of dividing the plurality of circuit elements.
    Type: Grant
    Filed: February 25, 2019
    Date of Patent: December 26, 2023
    Assignee: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Masahiro Fujikawa, Kunihiko Nishimura, Shuichi Hiza, Eiji Yagyu
  • Patent number: 11829837
    Abstract: In evaluation of the print quality of a symbol, the evaluation processing takes time. A symbol evaluation device (5) includes: a decoding unit (52) that decodes a symbol included in an image and thereby identifies reference position information of the symbol; a module position identification unit (53) that identifies a plurality of module positions included in the symbol on the basis of the reference position information of the symbol identified by the decoding unit; and a quality evaluation unit (54) that evaluates the quality of the symbol on the basis of the plurality of module positions identified by the module position identification unit.
    Type: Grant
    Filed: April 1, 2020
    Date of Patent: November 28, 2023
    Assignee: OMRON Corporation
    Inventor: Masahiro Fujikawa
  • Publication number: 20230290635
    Abstract: A provided is a polycrystalline diamond substrate that can reduce the cost for inhibiting warpage. The polycrystalline diamond substrate is a polycrystalline diamond substrate having a first principal surface and a second principal surface, and includes, between the first principal surface and the second principal surface, a surface having an average grain diameter smaller than each of average grain diameters of the first principal surface and the second principal surface.
    Type: Application
    Filed: September 18, 2020
    Publication date: September 14, 2023
    Applicant: Mitsubishi Electric Corporation
    Inventors: Ken IMAMURA, Masahiro FUJIKAWA, Kunihiko NISHIMURA, Eiji YAGYU
  • Publication number: 20230238296
    Abstract: A split in a dicing street in a semiconductor film is prevented. A semiconductor device includes: a first dicing street passing between a plurality of element regions on which a plurality of protective films are formed one-to-one, the first dicing street extending along a first axis; a second dicing street passing between the plurality of element regions and extending along a second axis; and a stop island disposed on the upper surface of the semiconductor film at an intersection between the first dicing street and the second dicing street, the stop island being in non-contact with the plurality of element regions. X_si>X_ds and Y_si<Y_ds are satisfied.
    Type: Application
    Filed: May 25, 2020
    Publication date: July 27, 2023
    Applicant: Mitsubishi Electric Corporation
    Inventors: Kunihiko NISHIMURA, Masahiro FUJIKAWA, Shuichi HIZA, Shinya NISHIMURA, Ken IMAMURA, Yuki TAKIGUCHI, Eiji YAGYU
  • Publication number: 20230134255
    Abstract: It is an object of the present disclosure to provide a method of manufacturing a thin semiconductor element having a low defect rate. A method of manufacturing a semiconductor element according to the present disclosure includes: forming a metal thin film on an electrode protection layer of a circuit element substrate and a support substrate in vacuum; attaching the metal thin film of the circuit element substrate and the metal thin film of the support substrate by an atomic diffusion joining method; removing a semiconductor substrate by polishing to expose a circuit element; joining a transfer substrate to an exposed surface of the circuit element; and detaching the support substrate from the circuit element after joining the transfer substrate.
    Type: Application
    Filed: April 13, 2020
    Publication date: May 4, 2023
    Applicant: Mitsubishi Electric Corporation
    Inventors: Masahiro FUJIKAWA, Eiji YAGYU
  • Publication number: 20220314357
    Abstract: Removal of substrates in a composite substrate is facilitated, and flaking of the composite substrate in an unintended process is prevented. A method for manufacturing a composite substrate includes: forming a first bonding material in a first surface of a first substrate; forming, in the first surface, at least one groove located more inward than a periphery in a plan view of the first substrate; forming the first bonding material along an inner wall of the at least one groove, the first bonding material not filling into space enclosed by the inner wall of the at least one groove; forming a second bonding material on a second surface of a second substrate; and bonding the first bonding material and the second bonding material together in a region except the at least one groove.
    Type: Application
    Filed: June 21, 2019
    Publication date: October 6, 2022
    Applicant: Mitsubishi Electric Corporation
    Inventors: Kunihiko NISHIMURA, Keisuke NAKAMURA, Masahiro FUJIKAWA, Shuichi HIZA, Tomohiro SHINAGAWA, Eiji YAGYU
  • Publication number: 20220230920
    Abstract: The present invention relates to a method for manufacturing a semiconductor substrate, including: (a) preparing an epitaxial substrate having a nitride semiconductor layer formed on a first main surface of a growth substrate and preparing a first support substrate, forming a resin adhesive layer between the first main surface of the growth substrate and a first main surface of the first support substrate, and bonding the epitaxial substrate to the first support substrate; (b) thinning a second main surface of the growth substrate; (c) forming a first protective thin film layer on the thinned growth substrate; (d) forming a second protective thin film layer on the first support substrate; (e) removing the thinned growth substrate; (0 bonding a second support substrate onto the nitride semiconductor layer; and (g) removing the first support substrate and the resin adhesive layer.
    Type: Application
    Filed: May 23, 2019
    Publication date: July 21, 2022
    Applicant: Mitsubishi Electric Corporation
    Inventors: Shuichi HIZA, Kunihiko NISHIMURA, Masahiro FUJIKAWA, Yuki TAKIGUCHI, Eiji YAGYU
  • Publication number: 20220188534
    Abstract: In evaluation of the print quality of a symbol, the evaluation processing takes time. A symbol evaluation device (5) includes: a decoding unit (52) that decodes a symbol included in an image and thereby identifies reference position information of the symbol; a module position identification unit (53) that identifies a plurality of module positions included in the symbol on the basis of the reference position information of the symbol identified by the decoding unit; and a quality evaluation unit (54) that evaluates the quality of the symbol on the basis of the plurality of module positions identified by the module position identification unit.
    Type: Application
    Filed: April 1, 2020
    Publication date: June 16, 2022
    Applicant: OMRON Corporation
    Inventor: Masahiro FUJIKAWA
  • Publication number: 20220171955
    Abstract: The present invention makes the identification of a border of a symbol less susceptible to the influence of disturbing noise, and reduces processing time. A symbol border identification device (5) which: identifies a reference position of an element constituting a symbol from decoding results of the symbol; determines whether a region is within the symbol on the basis of profile information that relates to the region and that is based on the reference position; and identifies a border of the symbol on the basis of a border element candidate identified in accordance with the determination result.
    Type: Application
    Filed: January 30, 2020
    Publication date: June 2, 2022
    Applicant: OMRON Corporation
    Inventor: Masahiro FUJIKAWA
  • Publication number: 20220059386
    Abstract: An object is to provide a technique capable of suppressing defectives in semiconductor elements. A manufacturing method of a semiconductor device includes a step of forming a laminated body in which an adhesive protective layer, an adhesive layer, a peeling layer, and a support substrate are disposed in this order on a first main surface of the semiconductor substrate, a step of removing the semiconductor substrate other than a portion where a plurality of circuit elements are formed, a step of bonding the portion where the circuit elements are formed to a transfer substrate, a step of removing the peeling layer, the support substrate and the adhesive layer, a step of removing the adhesive protective layer by chemical treatment, and a step of dividing the plurality of circuit elements.
    Type: Application
    Filed: February 25, 2019
    Publication date: February 24, 2022
    Applicant: Mitsubishi Electric Corporation
    Inventors: Masahiro FUJIKAWA, Kunihiko NISHIMURA, Shuichi HIZA, Eiji YAGYU
  • Patent number: 9998683
    Abstract: An image processing device is connected to an imaging unit. The imaging unit has an overlapping region in an imaging range before and after continuous imaging. The image processing device includes: an interface that receives a plurality of captured images obtained by the imaging unit; a measurement unit configured to acquire a measurement result of a subject in the captured image by performing measurement processing to the captured image; a synthesis unit configured to generate a synthesized image by synthesizing the plurality of captured images such that the captured images overlap with one another within an overlapping range corresponding to the overlapping region in imaging order; and an output unit configured to output the synthesized image, information indicating the overlapping range correlated with the synthesized image, and information indicating the measurement result.
    Type: Grant
    Filed: August 26, 2013
    Date of Patent: June 12, 2018
    Assignee: OMRON Corporation
    Inventors: Masahiro Fujikawa, Koji Shimada, Kakuto Shirane, Katsuhiro Shimoda, Yoshihiro Moritoki, Yasuyuki Ikeda, Hiroyuki Hazeyama
  • Patent number: 9607234
    Abstract: An image processing method improves the extraction accuracy of objects other than symbols. The image processing method may include four processes. In the first process, an image is input. In the second process, a symbol in the image is read. In the third process, a mask area including the symbol is set. In the fourth process, an object located in an area other than the mark area in the image is recognized.
    Type: Grant
    Filed: March 10, 2015
    Date of Patent: March 28, 2017
    Assignee: OMRON CORPORATION
    Inventors: Masahiro Fujikawa, Yasuyuki Ikeda, Yuki Akatsuka
  • Patent number: 9571795
    Abstract: An image processing device includes: an image receiving part configured to receive an image of a target workpiece on a surface of a conveying path captured by means of the imaging unit; a position acquiring part configured to acquire a position of the target workpiece in the captured image; a tilt acquiring part configured to acquire, by using the position of the target workpiece in the captured image acquired by means of the position acquiring part, a tilt angle of an imaging plane of the imaging unit relative to the surface of conveying path; and an outputting part configured to output assistant information used for assisting in the adjustment of the posture of the imaging unit by using the acquired tilt angle.
    Type: Grant
    Filed: August 26, 2013
    Date of Patent: February 14, 2017
    Assignee: OMRON Corporation
    Inventors: Masahiro Fujikawa, Koji Shimada, Kakuto Shirane, Katsuhiro Shimoda, Yoshihiro Moritoki, Yasuyuki Ikeda, Takeshi Yoshiura
  • Publication number: 20150262022
    Abstract: An image processing method improves the extraction accuracy of objects other than symbols. The image processing method may include four processes. In the first process, an image is input. In the second process, a symbol in the image is read. In the third process, a mask area including the symbol is set. In the fourth process, an object located in an area other than the mark area in the image is recognized.
    Type: Application
    Filed: March 10, 2015
    Publication date: September 17, 2015
    Inventors: Masahiro FUJIKAWA, Yasuyuki IKEDA, Yuki AKATSUKA
  • Patent number: 8831330
    Abstract: This invention provides a parameter determination assisting device and a parameter determination assisting program enabling a more rapid and easy determination of a parameter to be set in a processing device, which obtains a processing result by performing a process using a set of parameters defined in advance on image data obtained by imaging a measuring target object. A user can easily select an optimum parameter set when a determination result and a statistical output are displayed in a list for each of a plurality of trial parameter candidates. For instance, while trial numbers “2”, “4”, and “5”, in which the number of false detections is zero, can perform a stable process, the parameter set of the trial number “2” is comprehensively assumed as optimum since the trial number “2” can perform the process in the shortest processing time length.
    Type: Grant
    Filed: January 19, 2010
    Date of Patent: September 9, 2014
    Assignee: Omron Corporation
    Inventors: Masahiro Fujikawa, Daisuke Mitani, Masahiro Takayama, Katsuhiro Shimoda, Yoshihiro Moritoki
  • Publication number: 20140015956
    Abstract: An image processing device is connected to an imaging unit. The imaging unit has an overlapping region in an imaging range before and after continuous imaging. The image processing device includes: an interface that receives a plurality of captured images obtained by the imaging unit; a measurement unit configured to acquire a measurement result of a subject in the captured image by performing measurement processing to the captured image; a synthesis unit configured to generate a synthesized image by synthesizing the plurality of captured images such that the captured images overlap with one another within an overlapping range corresponding to the overlapping region in imaging order; and an output unit configured to output the synthesized image, information indicating the overlapping range correlated with the synthesized image, and information indicating the measurement result.
    Type: Application
    Filed: August 26, 2013
    Publication date: January 16, 2014
    Applicant: OMRON Corporation
    Inventors: Masahiro FUJIKAWA, Koji SHIMADA, Kakuto SHIRANE, Katsuhiro SHIMODA, Yoshihiro MORITOKI, Yasuyuki IKEDA, Hiroyuki HAZEYAMA
  • Publication number: 20140015957
    Abstract: An image processing device includes: an image receiving part configured to receive an image of a target workpiece on a surface of a conveying path captured by means of the imaging unit; a position acquiring part configured to acquire a position of the target workpiece in the captured image; a tilt acquiring part configured to acquire, by using the position of the target workpiece in the captured image acquired by means of the position acquiring part, a tilt angle of an imaging plane of the imaging unit relative to the surface of conveying path; and an outputting part configured to output assistant information used for assisting in the adjustment of the posture of the imaging unit by using the acquired tilt angle.
    Type: Application
    Filed: August 26, 2013
    Publication date: January 16, 2014
    Applicant: OMRON Corporation
    Inventors: Masahiro FUJIKAWA, Koji SHIMADA, Kakuto SHIRANE, Katsuhiro SHIMODA, Yoshihiro MORITOKI, Yasuyuki IKEDA, Takeshi YOSHIURA
  • Publication number: 20120236140
    Abstract: An user support apparatus includes a display unit configured to display an image obtained by image capturing with the image capturing unit, an input unit configured to receive a designation of a region of a workpiece to be detected in the image displayed on the display unit, and a determining unit configured to determine an image capturing start condition for the image capturing unit that is defined in terms of the amount of movement of a conveying apparatus, based on the size of the region indicating the workpiece to be detected by using a relationship between the image capturing range of the image capturing unit and the physical length of the conveying apparatus.
    Type: Application
    Filed: November 15, 2011
    Publication date: September 20, 2012
    Applicant: OMRON CORPORATION
    Inventors: Hiroyuki HAZEYAMA, Yasuyuki IKEDA, Masahiro FUJIKAWA, Naoya NAKASHITA
  • Publication number: 20120037224
    Abstract: A solar battery cell including: a semiconductor substrate; front-surface asperities formed on the principal surface on a light-receiving side of the semiconductor substrate; a semiconductor layer having a conductive type and formed along the front-surface asperities; and an anti-reflection film formed on the light-receiving side of the semiconductor layer, a passivation film is formed on the principal surface on the back-surface side of the semiconductor substrate, and at least one opening is provided in the passivation film. A first back-surface electrode is formed on the passivation film so as to overlap the entire area occupied by the opening and to cover the opening, and a second back-surface electrode is formed on the passivation film so as to overlap the entire area occupied by the first back-surface electrode and to cover the first back-surface electrode.
    Type: Application
    Filed: March 2, 2010
    Publication date: February 16, 2012
    Applicant: Mitsubishi Electric Corporation
    Inventors: Masahiro Fujikawa, Shigeru Matsuno