Abstract: An instruction processing apparatus including a processor configured to execute a process including issuing, by an instruction scheduler, instructions that can be executed; holding, by a register file, data used by the instructions; executing, by an execution unit including a plurality of stages, the instructions issued by the instruction scheduler; detecting, by a detector, early termination in which an execution result of an intermediate stage, which is before a final stage among the plurality of stages, is the same as an execution result of the execution unit; and transferring, by a bypass controller, the data output from the register file or the execution result from the execution unit, to an input of the execution unit, and in response to the detector detecting the early termination, bypassing the execution result of the intermediate stage to the input of the execution unit.

Abstract: A processor includes request issuing units issuing an access request to a storage, a data array including banks holding sub data divided from data read from the storage based on the access request, a switch to transfer the access request to one of the banks, and first and second determination units. The first determination unit determines a cache hit when a tag address included in the access address matches a tag address held therein in correspondence with an index address included in the access address. The second determination unit determines a cache hit when identification information corresponding to a first tag address included in the access address and a second tag address included in the access address, match identification information and second tag address held therein. A cache controller makes access to the data array or storage, based on a determination result of the first or second determination unit.

Abstract: A processor includes a queue configured to hold a memory access instruction including one or more addresses, a contracted address generator configured to generate a contracted address by contracting bits of multiple addresses in a case where the memory access instruction includes the multiple addresses, a conflict detector configured to detect a conflict between the contracted address and the address held in the queue, and an access controller configured to control processes of the memory access instruction held in the queue, based on a detection result of the conflict detector.

Abstract: A processor includes issuing units to issue a read access request to a storage, a cache including banks capable of holding first data divided from data read from the storage, a switch interconnecting the issuing units and the banks, and a data distribution unit disposed between the issuing units and the switch. The switch outputs one of read access requests to a bank that is a read target, when each of read target data of the read access requests issued from the issuing units is one of second data included in the first data, and the first data read from the bank is output to the data distribution unit. The data distribution unit outputs each of the second data, divided from the first data received from the switch, in parallel to an issuing unit that is an originator of the read access request.

Abstract: A processor includes request issuing units issuing an access request to a storage, a data array including banks holding sub data divided from data read from the storage based on the access request, a switch to transfer the access request to one of the banks, and first and second determination units. The first determination unit determines a cache hit when a tag address included in the access address matches a tag address held therein in correspondence with an index address included in the access address. The second determination unit determines a cache hit when identification information corresponding to a first tag address included in the access address and a second tag address included in the access address, match identification information and second tag address held therein. A cache controller makes access to the data array or storage, based on a determination result of the first or second determination unit.

Abstract: An operation processing apparatus including one or more lanes each of which processes at most one element operation of an instruction per cycle, and an element operation issuing unit that issues the element operation to the one or more lanes, wherein an entirety of the operation processing apparatus is separated into a plurality of sections by buffers including a plurality of entries, zero or more of the sections that are unable to continue processing of element operations stop the processing, and remaining sections each continue the processing of element operations by storing element operations proceeding to the downstream section into the immediately downstream buffer.

Abstract: An example of a device comprises a storage which stores data which is input from outside and to which tracking information is added, a section which detects a first reading event of first data from the storage to which the tracking information is added, a section which detects, after the first reading event, a first writing event to part of character string data to the storage, a section which detects, after the first writing event, a second reading event of second data from the storage to which the tracking information is added, a section which detects, after the second reading event, a second writing event to part of the character string data to the storage, and a section which adds, when the first reading/writing event, second reading/writing event are detected, the tracking information to data to be written to the storage by the first and second writing event.

Abstract: A data transfer apparatus and a data transfer system are provided that can reduce the cost of installing communication equipment compatible with each of several dissimilar communication protocols in one exchange office and can reduce the cost of constructing the network.

Abstract: An example of a device comprises a storage which stores data which is input from outside and to which tracking information is added, a section which detects a first reading event of first data from the storage to which the tracking information is added, a section which detects, after the first reading event, a first writing event to part of character string data to the storage, a section which detects, after the first writing event, a second reading event of second data from the storage to which the tracking information is added, a section which detects, after the second reading event, a second writing event to part of the character string data to the storage, and a section which adds, when the first reading/writing event, second reading/writing event are detected, the tracking information to data to be written to the storage by the first and second writing event.

Abstract: A data transfer apparatus and a data transfer system are provided that can reduce the cost of installing communication equipment compatible with each of several dissimilar communication protocols in one exchange office and can reduce the cost of constructing the network.