Patents by Inventor Masahiro Higuchi

Masahiro Higuchi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250027513
    Abstract: A rotating device includes a shaft, an impeller fixed to the shaft, a motor causing the impeller to rotate, and a casing accommodating the impeller and the motor. The casing includes a suction port and a discharge port for a fluid. The casing and a heat sink are adjacent in a radial direction of the impeller. The heat sink includes a first part adjacent to the discharge port and a second part disposed inside the discharge port. The first part is in contact with a heat pipe. The second part is in contact with the casing in an axial direction of the impeller.
    Type: Application
    Filed: July 16, 2024
    Publication date: January 23, 2025
    Inventors: Masahiro KITAGAWA, Yukihiro HIGUCHI
  • Publication number: 20250016473
    Abstract: A solid-state image capturing device includes a pixel which includes: a first photoelectric converter; a floating diffusion; a first charge accumulator including one electrode and an other electrode; a first transfer transistor including a source and a drain, one of which is connected to the first photoelectric converter and an other of which is connected to the floating diffusion; a second transfer transistor including a source and a drain, one of which is connected to the one electrode; a reset transistor including a source and a drain, one of which is connected to the other of the source and the drain of the second transfer transistor and an other of which is connected to a power supply line; and a switching transistor including a source and a drain, one of which is connected to the other electrode, and an other of which is connected to the power supply line.
    Type: Application
    Filed: September 17, 2024
    Publication date: January 9, 2025
    Inventors: Masahiro HIGUCHI, Yutaka ABE, Takayasu KITO
  • Publication number: 20240344931
    Abstract: An exhaust gas sampling device that collects an exhaust gas emitted from a vehicle including an engine or a part of the vehicle into a sampling bag includes a main channel through which the exhaust gas flows, a main valve that opens and shuts the main channel, a dilution gas channel that is connected downstream from the main valve in the main channel and introduces a dilution gas into the main channel, a purge gas channel that branches from the dilution gas channel and has a downstream end connected downstream from the main valve in the main channel and upstream from a junction of the dilution gas channel and a purge pump that is disposed in the purge gas channel, sucks a part of the dilution gas flowing through the dilution gas channel, and delivers the sucked part as a purge gas to the main channel.
    Type: Application
    Filed: October 3, 2022
    Publication date: October 17, 2024
    Applicant: HORIBA, LTD.
    Inventors: Takeshi KIMURA, Kazunori KURIAKI, Masahiro HIGUCHI, Yoji KOMATSU, Jun TOMITA
  • Publication number: 20230204475
    Abstract: A dilution gas mixing unit that is used in an exhaust gas analysis system that analyzes the mixed gas obtained by diluting an exhaust gas with the dilution gas, and mixes the dilution gas with the exhaust gas is provided with a dilution gas supply pipe that is connected to an exhaust gas introduction pipe into which the exhaust gas is introduced and supplies the dilution gas to the exhaust gas introduction pipe, a dilution gas sampling unit that is provided in the dilution gas supply pipe and collects the dilution gas, and a backflow prevention member that is provided closer to the exhaust gas introduction pipe than the dilution gas sampling unit in the dilution gas supply pipe and prevents the mixed gas from flowing backward through the dilution gas supply pipe.
    Type: Application
    Filed: July 1, 2021
    Publication date: June 29, 2023
    Applicant: HORIBA, LTD.
    Inventors: Masaaki YASUDA, Hiromitsu IZUMI, Takeshi KIMURA, Masahiro HIGUCHI
  • Patent number: 11343457
    Abstract: An output buffer of a super source follower for driving a reference ramp signal of a column-parallel single slope type ADC of a solid-state imaging device is made as a class AB feedback configuration for controlling a feedback variable current source with a signal obtained by amplifying a current fluctuation flowing through an amplification transistor by an amplifier, and thereby, the upper limit of the drain voltage of the amplification transistor is not limited by the voltage between the gate and the source of the feedback variable current source.
    Type: Grant
    Filed: May 12, 2020
    Date of Patent: May 24, 2022
    Assignee: NUVOTON TECHNOLOGY CORPORATION JAPAN
    Inventor: Masahiro Higuchi
  • Patent number: 10778921
    Abstract: A solid-state imaging device includes an A/D converter per column. The A/D converter performs a first A/D conversion that (i) refines, using a first comparator, a range including a potential of an analog signal to a range of a potential corresponding to a difference between a first potential and a second potential through a binary search, and further (ii) generates, based on a result of the binary search, a first digital signal being a high-order portion of a digital signal. The A/D converter also performs a second A/D conversion that generates, based on a ramp signal and the result of the binary search, a second digital signal being a low-order portion of a remainder of the digital signal, by measuring a time necessary for an output of a second comparator to be inverted.
    Type: Grant
    Filed: February 27, 2018
    Date of Patent: September 15, 2020
    Assignee: PANASONIC SEMICONDUCTOR SOLUTIONS CO., LTD.
    Inventors: Yutaka Abe, Kazuko Nishimura, Hiroshi Fujinaka, Masahiro Higuchi, Dai Ichiryu
  • Publication number: 20200275041
    Abstract: An output buffer of a super source follower for driving a reference ramp signal of a column-parallel single slope type ADC of a solid-state imaging device is made as a class AB feedback configuration for controlling a feedback variable current source with a signal obtained by amplifying a current fluctuation flowing through an amplification transistor by an amplifier, and thereby, the upper limit of the drain voltage of the amplification transistor is not limited by the voltage between the gate and the source of the feedback variable current source.
    Type: Application
    Filed: May 12, 2020
    Publication date: August 27, 2020
    Inventor: Masahiro HIGUCHI
  • Publication number: 20200036931
    Abstract: A solid-state imaging device includes an A/D converter per column. The A/D converter performs a first A/D conversion that (i) refines, using a first comparator, a range including a potential of an analog signal to a range of a potential corresponding to a difference between a first potential and a second potential through a binary search, and further (ii) generates, based on a result of the binary search, a first digital signal being a high-order portion of a digital signal. The A/D converter also performs a second A/D conversion that generates, based on a ramp signal and the result of the binary search, a second digital signal being a low-order portion of a remainder of the digital signal, by measuring a time necessary for an output of a second comparator to be inverted.
    Type: Application
    Filed: February 27, 2018
    Publication date: January 30, 2020
    Inventors: Yutaka ABE, Kazuko NISHIMURA, Hiroshi FUJINAKA, Masahiro HIGUCHI, Dai ICHIRYU
  • Publication number: 20190327129
    Abstract: A connection control apparatus includes a memory and a processor coupled to the memory. The processor is configured to identify, upon detecting a change of a state of one or more servers included in a server group, a server in a synchronous standby state with respect to a primary server after the detection of the change from servers included in the server group after the detection of the change. The processor is configured to request, upon receiving an access request from a terminal, the terminal to connect to the identified server.
    Type: Application
    Filed: March 28, 2019
    Publication date: October 24, 2019
    Applicant: FUJITSU LIMITED
    Inventors: Masahiro Higuchi, Toshiro Ono, Kazuhiro Taniguchi
  • Patent number: 10309889
    Abstract: An exhaust gas analysis system is adapted to include an exhaust gas circulation line through which exhaust gas flows, an exhaust gas collection line adapted to collect the exhaust gas from the exhaust gas circulation line and introduce the collected exhaust gas into an exhaust gas analysis device, a continuous analysis line adapted to, separately from the diluted exhaust gas collection line, collect the exhaust gas from the exhaust gas circulation line for continuous analysis, a continuous analyzer provided in the continuous analysis line, and an information processing unit adapted to, on the basis of an analysis result by the continuous analyzer at the time of the collection into the exhaust gas analysis device, determine whether a measurement result of the exhaust gas introduced into the exhaust gas analysis device falls within a preset range, or determine a measurement range used to measure the exhaust gas introduced into the exhaust gas analysis device.
    Type: Grant
    Filed: May 24, 2017
    Date of Patent: June 4, 2019
    Assignee: HORIBA, LTD.
    Inventors: Masatsune Tokuhira, Jungo Okada, Masahiro Higuchi
  • Publication number: 20170343462
    Abstract: An exhaust gas analysis system is adapted to include an exhaust gas circulation line through which exhaust gas flows, an exhaust gas collection line adapted to collect the exhaust gas from the exhaust gas circulation line and introduce the collected exhaust gas into an exhaust gas analysis device, a continuous analysis line adapted to, separately from the diluted exhaust gas collection line, collect the exhaust gas from the exhaust gas circulation line for continuous analysis, a continuous analyzer provided in the continuous analysis line, and an information processing unit adapted to, on the basis of an analysis result by the continuous analyzer at the time of the collection into the exhaust gas analysis device, determine whether a measurement result of the exhaust gas introduced into the exhaust gas analysis device falls within a preset range, or determine a measurement range used to measure the exhaust gas introduced into the exhaust gas analysis device.
    Type: Application
    Filed: May 24, 2017
    Publication date: November 30, 2017
    Applicant: HORIBA, Ltd.
    Inventors: Masatsune TOKUHIRA, Jungo OKADA, Masahiro HIGUCHI
  • Patent number: 9641774
    Abstract: A solid-state imaging device that suppresses streaking includes an imaging region in which unit cells are aligned in matrix, an A/D converter for converting an analog signal generated in the imaging region to a digital signal, and a ramp buffer having an input terminal and an output terminal. Ramp voltage is input to the input terminal, and a reference signal having the ramp voltage is output from the output terminal toward the A/D converter. The A/D converter includes a comparator disposed in each column for comparing an analog signal with a reference signal, and a counter disposed corresponding to the comparator for counting a comparison period of the comparator. The ramp buffer includes a feedback circuit for simultaneously outputting the reference signal to the multiple comparators and controlling the amount of current flowing to the output terminal according to the ramp voltage of the reference signal output from the terminal.
    Type: Grant
    Filed: March 17, 2016
    Date of Patent: May 2, 2017
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Sanshiro Shishido, Masahiro Higuchi, Dai Ichiryu, Kazuko Nishimura, Yutaka Abe
  • Patent number: 9629383
    Abstract: Provided is dried pasta having no or very little cracking and a manufacturing method therefor. The method for manufacturing dried pasta comprises a drying step of drying pasta noodle strands to reach the percentage of water content of 14% or less under an environment maintained at a temperature of 75 to 95° C. and humidity of 60 to 90%; a heating step of heating, after the drying step, the pasta noodle strands for 10 to 120 minutes under an environment maintained at a temperature lower by at least 15° C. than the temperature in the drying step and within a range of 50 to 80° C., and humidity of 60 to 90%; and a cooling step of cooling, after the heating step, the pasta noodle strands for 10 to 60 minutes under an environment maintained at a temperature of 20 to 40° C. and humidity of 40 to 80%.
    Type: Grant
    Filed: March 15, 2012
    Date of Patent: April 25, 2017
    Assignee: NISSHIN FOODS INC.
    Inventor: Masahiro Higuchi
  • Patent number: 9549135
    Abstract: A solid-state imaging device includes: a plurality of unit cells each including at least one light receiving unit and an amplifying transistor which outputs an amplified signal corresponding to an amount of the signal charge photoelectrically converted by the light receiving unit; a plurality of vertical signal lines each for receiving an output signal from the amplifying transistor; a pixel power supply line for supplying a power supply voltage to the amplifying transistor; a plurality of constant current source transistors each connected to a different one of the vertical signal lines; and a bias circuit which controls an amount of current to be supplied to each of the constant current source transistors, based on a variation in the power supply voltage.
    Type: Grant
    Filed: September 18, 2015
    Date of Patent: January 17, 2017
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Takayasu Kito, Hiroyuki Amikawa, Masahiro Higuchi, Kenichi Origasa, Hiroshi Fujinaka
  • Patent number: 9497398
    Abstract: The solid-state imaging device includes a D/A converting circuit generating a reference voltage to be used for an A/D conversion. The D/A converting circuit includes: a voltage generating circuit generating an analog voltage according to a digital signal; a buffer circuit (a resistor ladder upper voltage supplying buffer circuit) which buffers the generated analog voltage, the buffer circuit sampling and holding a bias voltage generated inside the buffer circuit, and outputting the buffered analog voltage using the held bias voltage; an analog signal outputting unit (a resistor ladder unit) outputting the reference voltage according to the inputted digital signal, by receiving an output from the buffer circuit; and a pre-charge amplifier which charges a noise-reducing capacitor in conjunction with the sampling and holding by the buffer circuit, the noise-reducing capacitor being connected to the analog signal outputting unit.
    Type: Grant
    Filed: January 21, 2016
    Date of Patent: November 15, 2016
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Sanshiro Shishido, Masahiro Higuchi
  • Patent number: 9420811
    Abstract: Provided are dried noodles having no or very little cracking and a manufacturing method therefor. The method for manufacturing dried noodles comprises a drying step of drying noodle strands to reach the percentage of water content of 15% or less under an environment maintained at a temperature of 30 to 50° C. and humidity of 60 to 80%; a cooling step of cooling, after the drying step, the noodle strands for 15 to 60 minutes under an environment maintained at a temperature of 15 to 25° C. and humidity of 40 to 70%; a packaging step of packaging, after the cooling step, the noodle strands; and a heating step of heating, after the packaging step, the noodle strands for 15 minutes to 120 minutes under an environment maintained at a temperature of 30 to 40° C.
    Type: Grant
    Filed: March 15, 2012
    Date of Patent: August 23, 2016
    Assignee: NISSHIN FOODS INC.
    Inventor: Masahiro Higuchi
  • Publication number: 20160205333
    Abstract: A solid-state imaging device that suppresses streaking includes an imaging region in which unit cells are aligned in matrix, an A/D converter for converting an analog signal generated in the imaging region to a digital signal, and a ramp buffer having an input terminal and an output terminal. Ramp voltage is input to the input terminal, and a reference signal having the ramp voltage is output from the output terminal toward the A/D converter. The A/D converter includes a comparator disposed in each column for comparing an analog signal with a reference signal, and a counter disposed corresponding to the comparator for counting a comparison period of the comparator. The ramp buffer includes a feedback circuit for simultaneously outputting the reference signal to the multiple comparators and controlling the amount of current flowing to the output terminal according to the ramp voltage of the reference signal output from the terminal.
    Type: Application
    Filed: March 17, 2016
    Publication date: July 14, 2016
    Inventors: SANSHIRO SHISHIDO, MASAHIRO HIGUCHI, DAI ICHIRYU, KAZUKO NISHIMURA, YUTAKA ABE
  • Patent number: 9374070
    Abstract: A ramp generator circuit includes: a reference signal generator circuit which generates a ramp waveform having a slope obtained by multiplication using a power of 2 according to a value of a higher order bit of a gain control signal; a clock control circuit which selectively outputs 2^m kinds of fractional-N clocks according to one of 2^m (natural number) areas obtained by dividing a code range represented by a lower order bit, when a negative gain is set; and a variable gain circuit which sets a ramp waveform according to the value of the gain control signal, and sets a ramp signal amplitude in each area so that a period ratio between ramp driving clocks for adjacent areas and a ratio between an amplitude of a ramp signal when the standard gain is set and a largest amplitude of a ramp signal are equal.
    Type: Grant
    Filed: November 24, 2014
    Date of Patent: June 21, 2016
    Assignee: PAANSONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Masahiro Higuchi, Hiroshi Fujinaka, Makoto Ikuma
  • Publication number: 20160142661
    Abstract: The solid-state imaging device includes a D/A converting circuit generating a reference voltage to be used for an A/D conversion. The D/A converting circuit includes: a voltage generating circuit generating an analog voltage according to a digital signal; a buffer circuit (a resistor ladder upper voltage supplying buffer circuit) which buffers the generated analog voltage, the buffer circuit sampling and holding a bias voltage generated inside the buffer circuit, and outputting the buffered analog voltage using the held bias voltage; an analog signal outputting unit (a resistor ladder unit) outputting the reference voltage according to the inputted digital signal, by receiving an output from the buffer circuit; and a pre-charge amplifier which charges a noise-reducing capacitor in conjunction with the sampling and holding by the buffer circuit, the noise-reducing capacitor being connected to the analog signal outputting unit.
    Type: Application
    Filed: January 21, 2016
    Publication date: May 19, 2016
    Inventors: Sanshiro SHISHIDO, Masahiro HIGUCHI
  • Patent number: 9282267
    Abstract: The solid-state imaging device includes a D/A converting circuit generating a reference voltage to be used for an A/D conversion. The D/A converting circuit includes: a voltage generating circuit generating an analog voltage according to a digital signal; a buffer circuit (a resistor ladder upper voltage supplying buffer circuit) which buffers the generated analog voltage, the buffer circuit sampling and holding a bias voltage generated inside the buffer circuit, and outputting the buffered analog voltage using the held bias voltage; an analog signal outputting unit (a resistor ladder unit) outputting the reference voltage according to the inputted digital signal, by receiving an output from the buffer circuit; and a pre-charge amplifier which charges a noise-reducing capacitor in conjunction with the sampling and holding by the buffer circuit, the noise-reducing capacitor being connected to the analog signal outputting unit.
    Type: Grant
    Filed: November 25, 2014
    Date of Patent: March 8, 2016
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Sanshiro Shishido, Masahiro Higuchi