Abstract: An electronic device comprised of a wiring board with a semiconductor component. The device is unlikely to have any defects, such as cracks to a solder joint portion during a reflow process of a flip-chip connection. The semiconductor component is flip-chip bonded at a pad array at a component side thereof to a pad array at a board side by way of an individual solder joint portion. In a solder resist layer at a semiconductor component side and a solder resist layer at a board side, D/D0 is prepared to be in a range of 0.70 to 0.99, where D is a bottom inner diameter of an opening at the board side and D0 is a bottom inner diameter of an opening at the component side.

Abstract: A method of producing a wiring board includes a preliminary plating step of forming a solder resist layer such that the main layer of each metal pad of the board is exposed in each corresponding opening and covering the surface of the exposed main layer with a preliminary Sn plated layer. A solder paste application step involves applying a solder paste, containing solder powder comprised of the high temperature Sn solder and thicker than the preliminary Sn plated layer, on the preliminary Sn plated layer. A subsequent solder melting step involves forming the Sn solder covering layer by melting the solder paste layer together with the preliminary Sn plated layer by heating the solder paste layer to a temperature higher than the liquid phase line temperature of the high temperature Sn solder. This wettingly extends the melted layers over the surface of the main layer.

Abstract: A method for fabricating a component board which includes forming a first main-face-side Au plating layer on surfaces of main-face-side connection terminals and a first back-face-side Au plating layer on surfaces of back-face-side connection terminals of the component board; covering the first main-face-side Au plating layer with a protection layer; forming a second back-face-side Au plating layer on the first back-face-side Au plating layer; and removing the protection layer after completing the second Au plating step. Alternatively, the first back-face-side Au plating layer may be removed after completing the masking step. Displacement Au plating is used as the first and second Au plating.

Abstract: A printed-wiring substrate 1 includes internal dielectric resin layers 12 and 14. A main-surface-side external dielectric resin layer 13 is formed on the internal dielectric resin layer 12 such that the surface thereof serves as a substrate main-surface 1A. A back-surface-side external dielectric resin layer 15 is formed on the internal dielectric resin layer 14 such that the surface thereof serves as a substrate back-surface 1B. A surface 12A of the main-surface-side internal dielectric resin layer 12 and a surface 14A of the back-surface-side internal dielectric resin layer 14 are roughened. The substrate main-surface 1A and the substrate back-surface 1B are roughened such that surface roughness thereof is lower than that of the surfaces 12A and 14A.

Abstract: A printed-wiring substrate 1 has main-face-side connection terminals 33 for solder-bonding to connection terminals 83 of an IC chip 81 on a main face 1A thereof and back-face-side connection terminals 41 for connecting, through mechanical contact, to connection terminals 93 of a motherboard 91 on a back face 1B thereof. The surface of each of the main-face-side connection terminals 33 is covered with a main-face-side displacement Au plating layer 45 having a thickness of 0.03 to 0.12 &mgr;m, and the surface of each of the back-face-side connection terminals 41 is covered with a back-face-side displacement Au plating layer 55, which is thicker than the main-face-side displacement Au plating layer 45 and has a thickness of 0.2 &mgr;m or greater.

Abstract: A process for producing a substrate 1 having a base-metal plating layer, which includes an immersion step for immersing the substrate 1 in a plating solution contained in a plating tank 33, to thereby form a base-metal plating layer; a washing step for removing the substrate 1 from the plating tank 33, transferring the substrate 1 to a washing tank, and washing the substrate 1; and a cooling step for applying a cooling liquid to the substrate 1 during at least a portion of the period during which the substrate is transferred to a position where the washing step is carried out after completing the immersion step, to thereby cool the substrate 1. An apparatus for carrying out the above process is also disclosed.

Abstract: A printed-wiring substrate 1 has main-face-side connection terminals 33 for solder-bonding to connection terminals 83 of an IC chip 81 on a main face 1A thereof and back-face-side connection terminals 41 for connecting, through mechanical contact, to connection terminals 93 of a motherboard 91 on a back face 1B thereof. The surface of each of the main-face-side connection terminals 33 is covered with a main-face-side displacement Au plating layer 45 having a thickness of 0.03 to 0.12 &mgr;m, and the surface of each of the back-face-side connection terminals 41 is covered with a back-face-side displacement Au plating layer 55, which is thicker than the main-face-side displacement Au plating layer 45 and has a thickness of 0.2 &mgr;m or greater.

Abstract: A process for producing a substrate 1 having a base-metal plating layer, which includes an immersion step for immersing the substrate 1 in a plating solution contained in a plating tank 33, to thereby form a base-metal plating layer; a washing step for removing the substrate 1 from the plating tank 33, transferring the substrate 1 to a washing tank, and washing the substrate 1; and a cooling step for applying a cooling liquid to the substrate 1 during at least a portion of the period during which the substrate is transferred to a position where the washing step is carried out after completing the immersion step, to thereby cool the substrate 1. An apparatus for carrying out the above process is also disclosed.

Abstract: A printed-wiring substrate 1 includes internal dielectric resin layers 12 and 14. A main-surface-side external dielectric resin layer 13 is formed on the internal dielectric resin layer 12 such that the surface thereof serves as a substrate main-surface 1A. A back-surface-side external dielectric resin layer 15 is formed on the internal dielectric resin layer 14 such that the surface thereof serves as a substrate back-surface 1B. A surface 12A of the main-surface-side internal dielectric resin layer 12 and a surface 14A of the back-surface-side internal dielectric resin layer 14 are roughened. The substrate main-surface 1A and the substrate back-surface 1B are roughened such that surface roughness thereof is lower than that of the surfaces 12A and 14A.

Abstract: A printed-wiring substrate 1 has main-face-side connection terminals 33 for solder-bonding to connection terminals 83 of an IC chip 81 on a main face 1A thereof and back-face-side connection terminals 41 for connecting, through mechanical contact, to connection terminals 93 of a motherboard 91 on a back face 1B thereof. The surface of each of the main-face-side connection terminals 33 is covered with a main-face-side displacement Au plating layer 45 having a thickness of 0.03 to 0.12 &mgr;m, and the surface of each of the back-face-side connection terminals 41 is covered with a back-face-side displacement Au plating layer 55, which is thicker than the main-face-side displacement Au plating layer 45 and has a thickness of 0.2 &mgr;m or greater.