Patents by Inventor Masahiro Ichitani
Masahiro Ichitani has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 7615872Abstract: A semiconductor device comprises: a package substrate having a plurality of bonding electrodes arranged in a peripheral region of a main surface thereof and wirings connected to the respective bonding electrodes and electrolessly plated; a semiconductor chip mounted on the package substrate; a plurality of wires connecting pads of the semiconductor chip and the bonding electrodes; a sealing body for sealing the semiconductor chip and the wires with resin; and a plurality of solder balls arranged on the package substrate. The wirings are formed only at the inner side of the plurality of bonding electrodes on the main surface of the package substrate, and no solder resist film is formed at the outer side of the plurality of bonding electrodes. With this arrangement, the region outside the bonding electrodes can be minimized and the semiconductor device can be downsized without changing the size of the chip mounted thereon.Type: GrantFiled: December 5, 2008Date of Patent: November 10, 2009Assignees: Renesas Technology Corp., Renesas Northern Japan Semiconductor, Inc.Inventors: Noriyuki Takahashi, Masahiro Ichitani, Rumiko Ichitani, legal representative, Kazuhiro Ichitani, legal representative, Sachiyo Ichitani, legal representative
-
Publication number: 20090091031Abstract: A semiconductor device comprises: a package substrate having a plurality of bonding electrodes arranged in a peripheral region of a main surface thereof and wirings connected to the respective bonding electrodes and electrolessly plated; a semiconductor chip mounted on the package substrate; a plurality of wires connecting pads of the semiconductor chip and the bonding electrodes; a sealing body for sealing the semiconductor chip and the wires with resin; and a plurality of solder balls arranged on the package substrate. The wirings are formed only at the inner side of the plurality of bonding electrodes on the main surface of the package substrate, and no solder resist film is formed at the outer side of the plurality of bonding electrodes. With this arrangement, the region outside the bonding electrodes can be minimized and the semiconductor device can be downsized without changing the size of the chip mounted thereon.Type: ApplicationFiled: December 5, 2008Publication date: April 9, 2009Inventors: Noriyuki Takahashi, Masahiro Ichitani, Rumiko Ichitani, Kazuhiro Ichitani, Sachiyo Ichitani
-
Patent number: 7479705Abstract: A semiconductor device comprises: a package substrate having a plurality of bonding electrodes arranged in a peripheral region of a main surface thereof and wirings connected to the respective bonding electrodes and electrolessly plated; a semiconductor chip mounted on the package substrate; a plurality of wires connecting pads of the semiconductor chip and the bonding electrodes; a sealing body for sealing the semiconductor chip and the wires with resin; and a plurality of solder balls arranged on the package substrate. The wirings are formed only at the inner side of the plurality of bonding electrodes on the main surface of the package substrate, and no solder resist film is formed at the outer side of the plurality of bonding electrodes. With this arrangement, the region outside the bonding electrodes can be minimized and the semiconductor device can be downsized without changing the size of the chip mounted thereon.Type: GrantFiled: August 27, 2004Date of Patent: January 20, 2009Assignee: Renesas Technology Corp.Inventors: Noriyuki Takahashi, Rumiko Ichitani, legal representative, Kazuhiro Ichitani, legal representative, Sachiyo Ichitani, legal representative, Masahiro Ichitani
-
Patent number: 7286386Abstract: A semiconductor device uses a package substrate on which bonding leads are formed respectively corresponding to bonding pads for address and data which are distributed to opposing first and second sides of a memory chip and address terminals and data terminals which are connected to the bonding leads. The semiconductor device further includes an address output circuit and a data input/output circuit which also serves for memory access and a signal processing circuit having a data processing function. A semiconductor chip having bonding pads connected to the bonding leads corresponding to the address terminals of the package substrate and bonding pads connected to the bonding leads corresponding to the data terminals of the package substrate and distributed to two sides out of four sides and the above-mentioned memory chip are mounted on the package substrate in a stacked structure.Type: GrantFiled: April 11, 2006Date of Patent: October 23, 2007Assignee: Renesas Technology Corp.Inventors: Takashi Miwa, Yasumi Tsutsumi, Masahiro Ichitani, Takanori Hashizume, Masamichi Sato, Naozumi Morino, Atsushi Nakamura, Saneaki Tamaki, Ikuo Kudo
-
Publication number: 20060180943Abstract: The present invention provides a semiconductor device having a stacked structure which realizes the miniaturization of a contour size and the reduction of thickness. The present invention also provides a semiconductor device which realizes high performance and high reliability in addition to the miniaturization of the contour size. The semiconductor device uses a package substrate on which bonding leads which are formed respectively corresponding to bonding pads for address and data which are distributed to opposing first and second sides of a memory chip and address terminals and data terminals which are connected to the bonding leads are formed. The semiconductor device further includes an address output circuit and a data input/output circuit which are also served for memory access and a signal processing circuit having a data processing function.Type: ApplicationFiled: April 11, 2006Publication date: August 17, 2006Inventors: Takashi Miwa, Yasumi Tsutsumi, Masahiro Ichitani, Takanori Hashizume, Masamichi Sato, Naozumi Morino, Atsushi Nakamura, Saneaki Tamaki, Ikuo Kudo
-
Patent number: 7061785Abstract: A semiconductor device uses a package substrate on which bonding leads are formed respectively corresponding to bonding pads for address and data which are distributed to opposing first and second sides of a memory chip and address terminals and data terminals which are connected to the bonding leads. The semiconductor device further includes an address output circuit and a data input/output circuit which also serves for memory access and a signal processing circuit having a data processing function. A semiconductor chip having bonding pads connected to the bonding leads corresponding to the address terminals of the package substrate and bonding pads connected to the bonding leads corresponding to the data terminals of the package substrate and distributed to two sides out of four sides and the above-mentioned memory chip are mounted on the package substrate in a stacked structure.Type: GrantFiled: June 27, 2003Date of Patent: June 13, 2006Assignee: Renesas Technology Corp.Inventors: Takashi Miwa, Yasumi Tsutsumi, Masahiro Ichitani, Takanori Hashizume, Masamichi Sato, Naozumi Morino, Atsushi Nakamura, Saneaki Tamaki, Ikuo Kudo
-
Patent number: 7015069Abstract: The back side of a strip substrate with plural semiconductor chips mounted thereon is vacuum-chucked to a lower mold half of a mold, and in this state the plural semiconductor chips are sealed with resin simultaneously to form a seal member. Thereafter, the strip substrate and the seal member are released from the mold and are cut into plural semiconductor devices. The semiconductor devices thus obtained are improved in their mounting reliability.Type: GrantFiled: February 2, 2005Date of Patent: March 21, 2006Assignees: Renesas Technology Corp., Hitachi ULSI Systems Co., Ltd., Hitachi Yonezawa Electronics Co., Ltd.Inventors: Noriyuki Takahashi, Masayuki Suzuki, Kouji Tsuchiya, Takao Matsuura, Takanori Hashizume, Masahiro Ichitani, Kazunari Suzuki, Takafumi Nishita, Kenichi Imura, Takashi Miwa
-
Patent number: 6919622Abstract: As the semiconductor chip is large-sized, highly integrated and speeded up, it becomes difficult to pack the semiconductor chip together with leads in a package. In view of this difficulty, there has been adopted the package structure called the “Lead-On-Chip” or “Chip-On-Lead” structure in which the semiconductor and the leads are stacked and packed. In the package of this structure, according to the present invention, the gap between the leading end portions of the inner leads and the semiconductor chip is made wider than that between the inner lead portions except the leading end portions and the semiconductor chip thereby to reduce the stray capacity, to improve the signal transmission rate and to reduce the electrical noises.Type: GrantFiled: February 10, 2004Date of Patent: July 19, 2005Assignee: Renesas Technology Corp.Inventors: Gen Murakami, Kunihiro Tsubosaki, Masahiro Ichitani, Kunihiko Nishi, Ichiro Anjo, Asao Nishimura, Makoto Kitano, Akihiro Yaguchi, Sueo Kawai, Masatsugu Ogata, Syuuji Eguchi, Hiroyoshi Kokaku, Masanori Segawa, Hiroshi Hozoji, Takashi Yokoyama, Noriyuki Kinjo, Aizo Kaneda, Junichi Saeki, Shozo Nakamura, Akio Hasebe, Hiroshi Kikuchi, Isamu Yoshida, Takashi Yamazaki, Kazuyoshi Oshima, Tetsuro Matsumoto
-
Publication number: 20050127535Abstract: The back side of a strip substrate with plural semiconductor chips mounted thereon is vacuum-chucked to a lower mold half of a mold, and in this state the plural semiconductor chips are sealed with resin simultaneously to form a seal member. Thereafter, the strip substrate and the seal member are released from the mold and are cut into plural semiconductor devices. The semiconductor devices thus obtained are improved in their mounting reliability.Type: ApplicationFiled: February 2, 2005Publication date: June 16, 2005Inventors: Noriyuki Takahashi, Masayuki Suzuki, Kouji Tsuchiya, Takao Matsuura, Takanori Hashizume, Masahiro Ichitani, Kazunari Suzuki, Takafumi Nishita, Kenichi Imura, Takashi Miwa
-
Patent number: 6887739Abstract: In a method of forming a ball grid array type semiconductor package, a semiconductor chip is mounted through an adhesive material on a surface of a flexible film substrate. Plural bump electrodes are arranged in an array on the opposite side of said substrate and the semiconductor chip is sealed by a resin. In this regard, an insulation layer is formed to cover an electric conductor layer pattern formed on the surface of the substrate, and the semiconductor chip is mounted through an adhesive material on the insulation layer. The insulation layer is divided into a plural number of parts that are mutually discontinuous in the area under the semiconductor chip. By this divided insulation layer, a short circuit between the semiconductor chip and the electric conductor layer pattern is prevented and a deformation of the substrate that comprises the flexible films is suppressed.Type: GrantFiled: July 3, 2003Date of Patent: May 3, 2005Assignees: Renesas Technology Corp., Hitachi Hokkai Semiconductor, Ltd.Inventors: Atsushi Fujisawa, Takafumi Konno, Shingo Ohsaka, Ryo Haruta, Masahiro Ichitani
-
Patent number: 6872597Abstract: The back side of a strip substrate with plural semiconductor chips mounted thereon is vacuum-chucked to a lower mold half of a mold, and in this state the plural semiconductor chips are sealed with resin simultaneously to form a seal member. Thereafter, the strip substrate and the seal member are released from the mold and are cut into plural semiconductor devices. The semiconductor devices thus obtained are improved in their mounting reliability.Type: GrantFiled: February 24, 2004Date of Patent: March 29, 2005Assignees: Renesas Technology Corp., Hitachi ULSI Systems Co., Ltd., Hitachi Yonezawa Electronics Co., Ltd.Inventors: Noriyuki Takahashi, Masayuki Suzuki, Kouji Tsuchiya, Takao Matsuura, Takanori Hashizume, Masahiro Ichitani, Kazunari Suzuki, Takafumi Nishita, Kenichi Imura, Takashi Miwa
-
Publication number: 20050046023Abstract: A semiconductor device comprises: a package substrate having a plurality of bonding electrodes arranged in a peripheral region of a main surface thereof and wirings connected to the respective bonding electrodes and electrolessly plated; a semiconductor chip mounted on the package substrate; a plurality of wires connecting pads of the semiconductor chip and the bonding electrodes; a sealing body for sealing the semiconductor chip and the wires with resin; and a plurality of solder balls arranged on the package substrate. The wirings are formed only at the inner side of the plurality of bonding electrodes on the main surface of the package substrate, and no solder resist film is formed at the outer side of the plurality of bonding electrodes. With this arrangement, the region outside the bonding electrodes can be minimized and the semiconductor device can be downsized without changing the size of the chip mounted thereon.Type: ApplicationFiled: August 27, 2004Publication date: March 3, 2005Applicants: Renesas Technology Corp., Renesas Northern Japan Semiconductor, Inc.Inventors: Noriyuki Takahashi, Masahiro Ichitani, Rumiko Ichitani
-
Publication number: 20040164428Abstract: The back side of a strip substrate with plural semiconductor chips mounted thereon is vacuum-chucked to a lower mold half of a mold, and in this state the plural semiconductor chips are sealed with resin simultaneously to form a seal member. Thereafter, the strip substrate and the seal member are released from the mold and are cut into plural semiconductor devices. The semiconductor devices thus obtained are improved in their mounting reliability.Type: ApplicationFiled: February 24, 2004Publication date: August 26, 2004Applicants: Renesas Technology Corp., Hitachi ULSI System Co., Ltd., Hitachi Yonezawa Electronics Co., Ltd.Inventors: Noriyuki Takahashi, Masayuki Suzuki, Kouji Tsuchiya, Takao Matsuura, Takanori Hashizume, Masahiro Ichitani, Kazunari Suzuki, Takafumi Nishita, Kenichi Imura, Takashi Miwa
-
Publication number: 20040155323Abstract: As the semiconductor chip is large-sized, highly integrated and speeded up, it becomes difficult to pack the semiconductor chip together with leads in a package. In view of this difficulty, there has been adopted the package structure called the “Lead-On-Chip” or “Chip-On-Lead” structure in which the semiconductor and the leads are stacked and packed. In the package of this structure, according to the present invention, the gap between the leading end portions of the inner leads and the semiconductor chip is made wider than that between the inner lead portions except the leading end portions and the semiconductor chip thereby to reduce the stray capacity, to improve the signal transmission rate and to reduce the electrical noises.Type: ApplicationFiled: February 10, 2004Publication date: August 12, 2004Inventors: Gen Murakami, Kunihiro Tsubosaki, Masahiro Ichitani, Kunihiko Nishi, Ichiro Anjo, Asao Nishimura, Makoto Kitano, Akihiro Yaguchi, Sueo Kawai, Masatsugu Ogata, Syuuji Eguchi, Hiroyoshi Kokaku, Masanori Segawa, Hiroshi Hozoji, Takashi Yokoyama, Noriyuki Kinjo, Aizo Kaneda, Junichi Saeki, Shozo Nakamura, Akio Hasebe, Hiroshi Kikuchi, Isamu Yoshida, Takashi Yamazaki, Kazuyoshi Oshima, Tetsuro Matsumoto
-
Patent number: 6764878Abstract: In a ball grid array type semiconductor package, a semiconductor chip is mounted through an adhesive material on a surface of a flexible film substrate. Plural bump electrodes are arranged in an array on the opposite side of said substrate and the semiconductor chip is sealed by a resin. In this regard, an insulation layer is formed to cover an electric conductor layer pattern formed on the surface of the substrate, and the semiconductor chip is mounted through an adhesive material on the insulation layer. The insulation layer is divided into a plural number of parts that are mutually discontinuous in the area under the semiconductor chip. By this divided insulation layer, a short circuit between the semiconductor chip and the electric conductor layer pattern is prevented and a deformation of the substrate that comprises the flexible films is suppressed.Type: GrantFiled: July 12, 2002Date of Patent: July 20, 2004Assignees: Renesas Technology Corp., Hitachi Hokkai Semiconductor, Ltd.Inventors: Atsushi Fujisawa, Takafumi Konno, Shingo Ohsaka, Ryo Haruta, Masahiro Ichitani
-
Patent number: 6759279Abstract: In a method of forming a ball grid array type semiconductor package, a semiconductor chip is mounted through an adhesive material on a surface of a flexible film substrate. Plural bump electrodes are arranged in an array on the opposite side of said substrate and the semiconductor chip is sealed by a resin. In this regard, an insulation layer is formed to cover an electric conductor layer pattern formed on the surface of the substrate, and the semiconductor chip is mounted through an adhesive material on the insulation layer. The insulation layer is divided into a plural number of parts that are mutually discontinuous in the area under the semiconductor chip. By this divided insulation layer, a short circuit between the semiconductor chip and the electric conductor layer pattern is prevented and a deformation of the substrate that comprises the flexible films is suppressed.Type: GrantFiled: August 8, 2002Date of Patent: July 6, 2004Assignees: Renesas Technology Corp., Hitachi Hokkai Semiconductor, Ltd.Inventors: Atsushi Fujisawa, Takafumi Konno, Shingo Ohsaka, Ryo Haruta, Masahiro Ichitani
-
Patent number: 6723583Abstract: The back side of a strip substrate with plural semiconductor chips mounted thereon is vacuum-chucked to a lower mold half of a mold, and in this state the plural semiconductor chips are sealed with resin simultaneously to form a seal member. Thereafter, the strip substrate and the seal member are released from the mold and are cut into plural semiconductor devices. The semiconductor devices thus obtained are improved in their mounting reliability.Type: GrantFiled: June 4, 2003Date of Patent: April 20, 2004Assignees: Renesas Technology Corp., Hitachi ULSI Systems Co. Ltd., Hitachi Yonezawa Electronics Co., Ltd.Inventors: Noriyuki Takahashi, Masayuki Suzuki, Kouji Tsuchiya, Takao Matsuura, Takanori Hashizume, Masahiro Ichitani, Kazunari Suzuki, Takafumi Nishita, Kenichi Imura, Takashi Miwa
-
Patent number: 6720208Abstract: As the semiconductor chip is large-sized, highly integrated and speeded up, it becomes difficult to pack the semiconductor chip together with leads in a package. In view of this difficulty, there has been adopted the package structure called the “Lead-On-Chip” or “Chip-On-Lead” structure in which the semiconductor and the leads are stacked and packed. In the package of this structure, according to the present invention, the gap between the leading end portions of the inner leads and the semiconductor chip is made wider than that between the inner lead portions except the leading end portions and the semiconductor chip thereby to reduce the stray capacity, to improve the signal transmission rate and to reduce the electrical noises.Type: GrantFiled: December 19, 2002Date of Patent: April 13, 2004Assignee: Renesas Technology CorporationInventors: Gen Murakami, Kunihiro Tsubosaki, Masahiro Ichitani, Kunihiko Nishi, Ichiro Anjo, Asao Nishimura, Makoto Kitano, Akihiro Yaguchi, Sueo Kawai, Masatsugu Ogata, Syuuji Eguchi, Hiroyoshi Kokaku, Masanori Segawa, Hiroshi Hozoji, Takashi Yokoyama, Noriyuki Kinjo, Aizo Kaneda, Junichi Saeki, Shozo Nakamura, Akio Hasebe, Hiroshi Kikuchi, Isamu Yoshida, Takashi Yamazaki, Kazuyoshi Oshima, Tetsuro Matsumoto
-
Publication number: 20040027869Abstract: The present invention provides a semiconductor device having a stacked structure which realizes the miniaturization of a contour size and the reduction of thickness. The present invention also provides a semiconductor device which realizes high performance and high reliability in addition to the miniaturization of the contour size. The semiconductor device uses a package substrate on which bonding leads which are formed respectively corresponding to bonding pads for address and data which are distributed to opposing first and second sides of a memory chip and address terminals and data terminals which are connected to the bonding leads are formed. The semiconductor device further includes an address output circuit and a data input/output circuit which are also served for memory access and a signal processing circuit having a data processing function.Type: ApplicationFiled: June 27, 2003Publication date: February 12, 2004Applicant: Hitachi, Ltd.Inventors: Takashi Miwa, Yasumi Tsutsumi, Masahiro Ichitani, Takanori Hashizume, Masamichi Sato, Naozumi Morino, Atsushi Nakamura, Saneaki Tamaki, Ikuo Kudo
-
Publication number: 20040005733Abstract: In a method of forming a ball grid array type semiconductor package, a semiconductor chip is mounted through an adhesive material on a surface of a flexible film substrate. Plural bump electrodes are arranged in an array on the opposite side of said substrate and the semiconductor chip is sealed by a resin. In this regard, an insulation layer is formed to cover an electric conductor layer pattern formed on the surface of the substrate, and the semiconductor chip is mounted through an adhesive material on the insulation layer. The insulation layer is divided into a plural number of parts that are mutually discontinuous in the area under the semiconductor chip. By this divided insulation layer, a short circuit between the semiconductor chip and the electric conductor layer pattern is prevented and a deformation of the substrate that comprises the flexible films is suppressed.Type: ApplicationFiled: July 3, 2003Publication date: January 8, 2004Inventors: Atsushi Fujisawa, Takafumi Konno, Shingo Ohsaka, Ryo Haruta, Masahiro Ichitani