Abstract: A semiconductor integrated circuit device with a buffer circuit is disclosed, which comprises a pre-buffer configured to receive an input signal from a front-stage circuit, a drive buffer having a first PMOS transistor and a first NMOS transistor connected in series between a power supply node and a ground node, the first PMOS and NMOS transistors having gates for receiving an output signal of the pre-buffer, a series-connection node of the first PMOS and NMOS transistors being connected to the output node, and a back-up buffer having a second PMOS transistor and a second NMOS transistor connected in series between the power supply node and the ground node, a series-connection node of the second PMOS and NMOS transistors being connected to the output node, one of the second PMOS and NMOS transistors is turned on after the other is turned off when the drive buffer is in a switching operation.

Abstract: A semiconductor integrated circuit device with a buffer circuit is disclosed, which comprises a pre-buffer configured to receive an input signal from a front-stage circuit, a drive buffer having a first PMOS transistor and a first NMOS transistor connected in series between a power supply node and a ground node, the first PMOS and NMOS transistors having gates for receiving an output signal of the pre-buffer, a series-connection node of the first PMOS and NMOS transistors being connected to the output node, and a back-up buffer having a second PMOS transistor and a second NMOS transistor connected in series between the power supply node and the ground node, a series-connection node of the second PMOS and NMOS transistors being connected to the output node, one of the second PMOS and NMOS transistors is turned on after the other is turned off when the drive buffer is in a switching operation.

Abstract: A power on reset circuit includes a charge and discharge circuit for performing charge or discharge operation on the basis of a potential obtained by dividing a power supply voltage using a potential divider circuit. The potential thus outputted is held by a first latch circuit to output a reset on signal or a reset off signal. The output state of the charge and discharge circuit is inverted to the power supply voltage on the basis of the output potential of the first latch circuit using a second latch circuit, which comprises the minimum number of elements including a NAND gate, an inverter and two capacitors. Thus, the power on reset circuit can obtain a stable reset signal if the initial state of the reset signal output is in either the power supply voltage level or the ground level.