Abstract: A semiconductor integrated circuit has an internal clock signal generator circuit and a data input/output circuit. The internal clock signal generator circuit includes a clock receiver, a synchronous delay control circuit, a clock driver, an output control circuit, a delay monitor, and a control signal generator circuit. Accordingly, in a delay measuring mode, a delay in the input signal is set in the delay monitor based on a measurement start signal and a measurement stop signal. After completion of the delay measuring mode, the delay monitor causes the signal CLK, outputted from the clock receiver, to lag behind by a delay set in the delay measuring mode. Further, the delay monitor outputs the delayed signal to the synchronous delay control circuit.

Abstract: A delay line for forward pulse has a plurality of delay units for forward pulse. A delay line for backward pulse has a plurality of delay units for backward pulse. In the delay line for backward pulse, a pulse signal is propagated in an opposite direction to a direction of the propagation in the delay line for forward pulse. A direction from an input terminal to an output terminal in the delay units for forward pulse is set to be parallel to a direction of the delay line for forward pulse. A direction from an input terminal to an output terminal in the delay units for backward pulse is set to be parallel to a direction of the delay line for backward pulse. The directions from the input terminal to the output terminal in two adjacent ones of the delay units for forward pulse are set to be opposite to one another. The directions from the input terminal to the output terminal in two adjacent ones of the delay units for backward pulse are set to be opposite to one another.

Abstract: A clock synchronous circuit comprising a clock receiver, a delay monitor, a forward pulse delay circuit, a backward pulse delay circuit, a driver, a state-holding section, a control signal generating circuit, a first AND circuit, and a second AND circuit. The delay monitor delays the output of the clock receiver. The forward pulse delay circuit delays the output of the delay monitor. The backward pulse delay circuit delays the output of the clock receiver. The driver receives the output of the backward pulse delay circuit and outputs an internal clock signal. The state-holding section controls the backward pulse delay circuit. The control pulse generating circuit initializes the forward pulse delay circuit. The first AND circuit is provided for controlling the supply of the output of the clock receiver to the delay monitor. The second AND is provided for controlling the supply of the output of the delay monitor to the forward pulse delay circuit.

Abstract: A clock control circuit includes a forward pulse delay circuit including a plurality of delay circuits for delaying a forward pulse signal FCL, a backward pulse delay circuit including a plurality of delay circuits for delaying a backward pulse signal RCL, a state-hold section including a plurality of state-hold circuits for controlling the operation of the backward pulse delay circuit in accordance with the transmission condition of the forward pulse signal in the forward pulse delay circuit, and an input stop circuit for stopping inputting a pulse corresponding to an external clock signal to the backward pulse delay circuit during a predetermined period from the time point when the external clock signal begins to be supplied.

Abstract: A cycle measuring circuit 3 measures a cycle of an external clock signal, which is approximately m times a unit time. A number converting circuit 5 and a time converting circuit 7 cooperate, generating a pulse signal delayed by m/2.sup.K times the unit time, or by 1/2.sup.K times the cycle of the external clock signal. A logic circuit 8 generates an internal clock signal which rises in synchronism with the external clock signal and falls in synchronism with the pulse signal thus delayed. Hence, the internal clock signal has the same cycle as the external clock signal and has a desired duty ratio of (1/2.sup.K).times.100%.