Abstract: This invention provides a multistage frequency multiplier having a plurality of frequency doublers. Each doubler incorporates a three-terminal transistor device and is connected to an adjacent doubler via an interstage network. The network comprises a transmission line having its electrical parameters selected to achieve conjugate impedance matching at the intermediate harmonic frequency generated by the corresponding doubler. This network also includes a quarter-wavelength open-ended stub for suppressing a main input frequency component received by the corresponding frequency doubler. A shunt resistor on the transistor gate is preferably used to stabilize the network. This interstage network simplifies overall circuit topology to reduce total circuit size, and provides increased drive power levels to permit broader bandwidth and stabilize required output level from a local oscillator.