Abstract: A semiconductor device has a substrate, an insulating interlayer, an interconnect as one example of an electro-conductive pattern, a through-electrode, and a bump as one example of a connection terminal, wherein the insulating interlayer is positioned up above the surface of the substrate, the interconnect is positioned on the surface of the insulating interlayer, the through-electrode extends through the substrate and the insulating interlayer, from the back surface of the former to the surface of the latter, one end of which is connected to the interconnect, and the bump is provided on the back surface side of the substrate, and connected to the other end of the through-electrode.

Abstract: The present invention provides a semiconductor device including at least one of an insulating layer and a semiconductor layer each including a hole formed therein, and a through electrode provided in the hole. In the semiconductor device, the side wall of the hole is constituted of a first region from the opening of the hole to a predetermined position between the opening of the hole and the bottom surface of the hole, and a second region from the predetermined position to the bottom surface of the hole. The through electrode includes a seed layer and a plating layer. The seed layer covers the second region and the bottom surface of the hole without covering the first region. In addition, the plating layer covers the seed layer and at least a part of the first region.

Abstract: A through electrode that offers excellent performance and can be manufactured through a simple process is to be provided. In a silicon spacer including a silicon substrate, an insulative thick film is provided so as to be in contact with a surface of the silicon substrate and a side wall of a through hole penetrating the silicon substrate. An upper surface of a through plug is retreated to a lower level than an interface between the silicon substrate and the insulative thick film, thus to define a height gap. A first bump is then formed, which is connected to the retreated surface of the through plug and has a larger diameter than that of the through plug at the upper surface of the insulative thick film.

Abstract: A semiconductor device includes an interconnect member, a first semiconductor chip, a second semiconductor chip, a resin layer, an inorganic insulating layer, and a through electrode. The first semiconductor chip is mounted in a face-down manner on the interconnect member. The resin layer covers the side surface of the first semiconductor chip. This inorganic insulating layer is in contact with the back surface of the first semiconductor chip, and directly covers the back surface. Also, the inorganic insulating layer extends over the resin layer. The through electrode penetrates the inorganic insulating layer and the semiconductor substrate of the first semiconductor chip. The second semiconductor chip is mounted in a face-down manner on the inorganic insulating layer that covers the back surface of the first semiconductor chip in the uppermost layer.

Abstract: A semiconductor device having a multilayer interconnection structure includes a chip semiconductor substrate, a plurality of interlayer insulating layers disposed on the chip semiconductor substrate, a circuit section disposed on the chip semiconductor substrate, and a plurality of walls that extend through the interlayer insulating layers and are arranged along the peripheral portions of the chip semiconductor substrate such that the walls surround the circuit section. The walls include upper sub-walls and lower sub-walls. The upper sub-walls extend through one of the interlayer insulating layers and further extend into another one of the interlayer insulating layers disposed under the layer through which the upper sub-walls extend. The lower sub-walls extend through one of the interlayer insulating layers disposed under the layer through which the upper sub-walls extend. Lower portions of the upper sub-walls each extend into corresponding upper portions of the lower sub-walls.

Abstract: A through electrode that offers excellent performance and can be manufactured through a simple process is to be provided. In a silicon spacer including a silicon substrate, an insulative thick film is provided so as to be in contact with a surface of the silicon substrate and a side wall of a through hole penetrating the silicon substrate. An upper surface of a through plug is retreated to a lower level than an interface between the silicon substrate and the insulative thick film, thus to define a height gap. A first bump is then formed, which is connected to the retreated surface of the through plug and has a larger diameter than that of the through plug at the upper surface of the insulative thick film.

Abstract: In a semiconductor device, a circuit unit is formed in an inside portion, and seal rings that enclose the inside portion that are composed of walls of metal layers are formed around the periphery. In the corners, the seal rings include linear parts that extend inwardly in addition to the linear parts that extend along the periphery, whereby the seal rings are formed in a planar pattern having small rectangular planar patterns in each corner.

Abstract: A semiconductor apparatus includes an under layer, a first insulating layer and a first conductive portion. The under layer is formed above a substrate. The first insulating layer is formed on the under layer. The first conductive portion is formed in a first concave portion which passes through the first insulating layer to the under layer. The first conductive portion includes a first barrier metal layer and a first metal portion. The first barrier metal layer is formed on a side wall and a bottom surface of the first concave portion. The first metal portion is formed on the first barrier metal layer such that the rest of the first concave portion is filled with the first metal portion. The first metal portion includes a first alloy including copper and aluminium.

Abstract: A semiconductor device having a multilayer interconnection structure includes a chip semiconductor substrate, a plurality of interlayer insulating layers disposed on the chip semiconductor substrate, a circuit section disposed on the chip semiconductor substrate, and a plurality of walls that extend through the interlayer insulating layers and are arranged along the peripheral portions of the chip semiconductor substrate such that the walls surround the circuit section. The walls include upper sub-walls and lower sub-walls. The upper sub-walls extend through one of the interlayer insulating layers and further extend into another one of the interlayer insulating layers disposed under the layer through which the upper sub-walls extend. The lower sub-walls extend through one of the interlayer insulating layers disposed under the layer through which the upper sub-walls extend. Lower portions of the upper sub-walls each extend into corresponding upper portions of the lower sub-walls.

Abstract: A semiconductor device is provided which is capable of preventing corrosion of circuit portion and ensuring high reliability by optimizing a construction of outer-surrounding protecting walls that surround an internal element region to completely stop invasion of water from an edge portion of a semiconductor chip. The outer-surrounding protecting walls made up of a wiring layer and a via layer are formed in a manner to surround the internal element region and that a distance between an edge portion of the semiconductor chip and the outermost-surrounding protecting wall is 30 &mgr;m. The outer-surrounding protecting wall is so formed as to doubly or more surround the internal element region.

Abstract: In a semiconductor device, a circuit unit is formed in an inside portion, and seal rings that enclose the inside portion that are composed of walls of metal layers are formed around the periphery. In the corners, the seal rings include linear parts that extend inwardly in addition to the linear parts that extend along the periphery, whereby the seal rings are formed in a planar pattern having small rectangular planar patterns in each corner.

Abstract: A semiconductor apparatus includes an under layer, a first insulating layer and a first conductive portion. The under layer is formed above a substrate. The first insulating layer is formed on the under layer. The first conductive portion is formed in a first concave portion which passes through the first insulating layer to the under layer. The first conductive portion includes a first barrier metal layer and a first metal portion. The first barrier metal layer is formed on a side wall and a bottom surface of the first concave portion. The first metal portion is formed on the first barrier metal layer such that the rest of the first concave portion is filled with the first metal portion. The first metal portion includes a first alloy including copper and aluminium.

Abstract: As an outside box mark for automatic overlay measurement formed on a semiconductor substrate, a # shape is formed by laying two vertical lines formed by word lines over two parallel lines formed of bit lines. Thereby, a misalignment value in the word line direction and a misalignment value in the bit line direction are measured simultaneously by using one box mark. When forming capacity contacts between wiring lines of a #-shaped structure formed of word lines and bit lines, it is conducted by using a box mark for automatic overlay measurement. As a result, it becomes possible to shorten the time required for measuring the misalignment values in the X direction (word lines) and Y direction (bit lines) and analyzing the measurement result.

Abstract: First, a conductive layer is formed on a semiconductor substrate having an alignment mark formed thereon. Next, a photoresist is selectively formed on a region of the conductive layer in which a wiring layer is to be formed and on the alignment mark. Subsequently, the conductive layer is etched by using the photoresist as a mask.

Abstract: A fabrication method for a semiconductor device is provided, which is able to increase pattern-to pattern lithography overlay accuracy. After a first layer made of a first material is formed, first and second slits serving as a first alignment mark are formed in the first layer. The first and second slits are spaced with a specific distance and are approximately parallel to each other. Each of the first and second slits is filled with a second material. Then, a second layer made of a third material is formed on the first layer. Subsequently, a mask is formed on the second layer. The mask has a first pattern serving as a second alignment mark. The second alignment mark is overlapped with the first and second slits serving as the first alignment mark. Preferably, the first alignment mark provides the main scale of a caliper, and the second alignment mark provides the vernier scale of the caliper.

Abstract: As an outside box mark for automatic overlay measurement formed on a semiconductor substrate, a # shape is formed by laying two vertical lines formed by word lines over two parallel lines formed of bit lines. Thereby, a misalignment value in the word line direction and a misalignment value in the bit line direction are measured simultaneously by using one box mark. When forming capacity contacts between wiring lines of a #-shaped structure formed of word lines and bit lines, it is conducted by using a box mark for automatic overlay measurement. As a result, it becomes possible to shorten the time required for measuring the misalignment values in the X direction (word lines) and Y direction (bit lines) and analyzing the measurement result.

Abstract: As an outside box mark for automatic overlay measurement formed on a semiconductor substrate, a (#) shape is formed by laying two vertical lines formed by word lines over two parallel lines formed of bit lines. Thereby, a misalignment value in the word line direction and a misalignment value in the bit line direction are measured simultaneously by using one box mark. When forming capacity contacts between wiring lines of a (#)-shaped structure formed of word lines and bit lines, it is conducted by using a box mark for automatic overlay measurement. As a result, it becomes possible to shorten the time required for measuring the misalignment values in the X direction (word lines) and Y direction (bit lines) and analyzing the measurement result.

Abstract: In a method of manufacturing a semiconductor device, MOS transistors are formed on a semiconductor substrate. Each of the MOS transistors includes impurity diffusion regions and a gate electrode. A first interlayer insulating film is deposited over the MOS transistors. Contact holes are opened in the first interlayer insulating film so as to reach the impurity diffusion regions. A conductor is deposited on an entire surface of the semiconductor substrate. The deposited conductor is etched back in order to form contact plugs only in the contact holes. Pad portions are formed only on the contact plugs by the use of a selective growth method. A capacitor is formed over the semiconductor substrate so as to be connected to the pad potions via capacitor contacts.

Abstract: A fabrication method for a semiconductor device is provided, which is able to increase pattern-to-pattern lithography overlay accuracy. After a first layer made of a first material is formed, first and second slits serving as a first alignment mark are formed in the first layer. The first and second slits are spaced with a specific distance and are approximately parallel to each other. Each of the first and second slits is filled with a second material. Then, a second layer made of a third material is formed on the first layer. Subsequently, a mask is formed on the second layer. The mask has a first pattern serving as a second alignment mark. The second alignment mark is overlapped with the first and second slits serving as the first alignment mark. Preferably, the first alignment mark provides the main scale of a caliper, and the second alignment mark provides the vernier scale of the caliper.