Abstract: A processor includes: an address generating unit that, when an instruction decoded by a decoding unit is an instruction to execute arithmetic processing on a plurality of operand sets each including a plurality of operands that are objects of the arithmetic processing, in parallel a plurality of times, generates an address set corresponding to each of the operand sets of the arithmetic processing for each time, based on a certain address displacement with respect to the plurality of operands included in each of the operand sets; a plurality of instruction queues that hold the generated address sets corresponding to the respective operand sets, in correspondence to respective processing units; and a plurality of processing units that perform the arithmetic processing in parallel on the operand sets obtained based on the respective address sets outputted by the plurality of instruction queues.

Abstract: An arithmetic processing device includes, a memory that stores a first data and a second data, a plurality of arithmetic circuits, a first memory arranged for each of the arithmetic circuits and that stores a first predetermined row having the predetermined number of the first data stored in the memory, a second memory arranged for each of the arithmetic circuits and that stores a second predetermined row having a predetermined number of the second data stored in the memory, and a plurality of multiply-add arithmetic circuits arranged for each of the arithmetic circuits, a number of the multiply-add arithmetic circuits corresponding to the predetermined number, each of the multiply-add arithmetic circuits that obtains a third data by executing the operation using the first data and the second data based on a result of performing a row operation which is an operation of one row of the first data.

Abstract: Each of product-sum arithmetic units 501 to 503 acquires, from a register file 410, different pieces of first element data included in a first predetermined row of first data that forms a matrix; acquires, from a register file 420, same pieces of second element data included in a second predetermined row of second data that forms a matrix; performs a row portion operation that is an operation performed on the first data by an amount corresponding to a single row by performing a process of performing an operation using the acquired first element data and the second element data; and performs an operation by using the first data and the second data based on the result of the row portion operation.

Abstract: A memory 11 stores therein first data and second data each of which has element data that forms a matrix. Arithmetic units 51 to 53 repeat, for each of a first predetermined row of the first data and a second predetermined row of the second data that are stored in the memory 11, by using the element data included in the first predetermined row and the element data included in the second predetermined row, a row portion operation based on the number of columns in the second data and performs, by using results of the row portion operations, an arithmetic operation process that acquires the operation results of the operation that uses the first data and the second data.

Abstract: A memory 11 stores therein first data and second data each of which has element data that forms a matrix. Arithmetic units 51 to 53 repeat, for each of a first predetermined row of the first data and a second predetermined row of the second data that are stored in the memory 11, by using the element data included in the first predetermined row and the element data included in the second predetermined row, a row portion operation based on the number of columns in the second data and performs, by using results of the row portion operations, an arithmetic operation process that acquires the operation results of the operation that uses the first data and the second data.

Abstract: An arithmetic processing apparatus, includes: an arithmetic operation execution circuit configured to execute an arithmetic operation; a first register configured to store data to be used for an arithmetic operation by the arithmetic operation execution circuit; a first buffer configured to store data; a first controller configured to store, when an array of data is changed and the changed data is stored into the first register as the data to be used for the arithmetic operation, a plurality of data groups, which are successively received, into the first buffer; and a second controller configured to successively output, every time each of the plurality of data groups is stored into the first buffer, data included in the data groups stored in the first buffer to the first register.

Abstract: A memory 11 stores therein first data and second data each of which has element data that forms a matrix. Arithmetic units 51 to 53 repeat, for each of a first predetermined row of the first data and a second predetermined row of the second data that are stored in the memory 11, by using the element data included in the first predetermined row and the element data included in the second predetermined row, a row portion operation based on the number of columns in the second data and performs, by using results of the row portion operations, an arithmetic operation process that acquires the operation results of the operation that uses the first data and the second data.

Abstract: An information processing apparatus includes a plurality of arithmetic processing apparatuses each of which is coupled to a first plurality of other arithmetic processing apparatuses among the plurality of arithmetic processing apparatuses via a first path and a second path, to a second plurality of other arithmetic processing apparatuses among the plurality of arithmetic processing apparatuses via a third path. Each of the plurality of arithmetic processing apparatuses includes first positional information on the first path, second positional information on the second path, and third positional information on the third path.

Abstract: A plurality of floating-point registers store data therein. A processing execution unit executes arithmetic processing by using data stored in the floating-point registers. A first switch and a second switch select a route connecting the processing execution unit and the floating-point registers. A switch control unit controls the first switch and the second switch so as to switch a route to be selected, based on a switching instruction from the processing execution unit.

Abstract: An arithmetic processing device includes, a memory that stores a first data and a second data, a plurality of arithmetic circuits, a first memory arranged for each of the arithmetic circuits and that stores a first predetermined row having the predetermined number of the first data stored in the memory, a second memory arranged for each of the arithmetic circuits and that stores a second predetermined row having a predetermined number of the second data stored in the memory, and a plurality of multiply-add arithmetic circuits arranged for each of the arithmetic circuits, a number of the multiply-add arithmetic circuits corresponding to the predetermined number, each of the multiply-add arithmetic circuits that obtains a third data by executing the operation using the first data and the second data based on a result of performing a row operation which is an operation of one row of the first data.

Abstract: An arithmetic processing apparatus, includes: an arithmetic operation execution circuit configured to execute an arithmetic operation; a first register configured to store data to be used for an arithmetic operation by the arithmetic operation execution circuit; a first buffer configured to store data; a first controller configured to store, when an array of data is changed and the changed data is stored into the first register as the data to be used for the arithmetic operation, a plurality of data groups, which are successively received, into the first buffer; and a second controller configured to successively output, every time each of the plurality of data groups is stored into the first buffer, data included in the data groups stored in the first buffer to the first register.

Abstract: Each of product-sum arithmetic units 501 to 503 acquires, from a register file 410, different pieces of first element data included in a first predetermined row of first data that forms a matrix; acquires, from a register file 420, same pieces of second element data included in a second predetermined row of second data that forms a matrix; performs a row portion operation that is an operation performed on the first data by an amount corresponding to a single row by performing a process of performing an operation using the acquired first element data and the second element data; and performs an operation by using the first data and the second data based on the result of the row portion operation.

Abstract: A memory 11 stores therein first data and second data each of which has element data that forms a matrix. Arithmetic units 51 to 53 repeat, for each of a first predetermined row of the first data and a second predetermined row of the second data that are stored in the memory 11, by using the element data included in the first predetermined row and the element data included in the second predetermined row, a row portion operation based on the number of columns in the second data and performs, by using results of the row portion operations, an arithmetic operation process that acquires the operation results of the operation that uses the first data and the second data.

Abstract: A plurality of floating-point registers store data therein. A processing execution unit executes arithmetic processing by using data stored in the floating-point registers. A first switch and a second switch select a route connecting the processing execution unit and the floating-point registers. A switch control unit controls the first switch and the second switch so as to switch a route to be selected, based on a switching instruction from the processing execution unit.

Abstract: A processor includes: an address generating unit that, when an instruction decoded by a decoding unit is an instruction to execute arithmetic processing on a plurality of operand sets each including a plurality of operands that are objects of the arithmetic processing, in parallel a plurality of times, generates an address set corresponding to each of the operand sets of the arithmetic processing for each time, based on a certain address displacement with respect to the plurality of operands included in each of the operand sets; a plurality of instruction queues that hold the generated address sets corresponding to the respective operand sets, in correspondence to respective processing units; and a plurality of processing units that perform the arithmetic processing in parallel on the operand sets obtained based on the respective address sets outputted by the plurality of instruction queues.

Abstract: A processor includes: a storage unit that stores instructions; a counting unit that specifies an instruction to be decoded by a count value; a decoding unit that decodes an instruction; and a control unit that, when the decoded instruction is a repeat instruction, updates the count value of the counting unit so as to cause repeat target instructions in number corresponding to a designated number of instructions, out of instructions succeeding the repeat instruction, to be repeatedly executed a designated number of repetition times, and generates updated operands being operation objects of the repeat target instructions that are to be executed for the second or later time, and when the repeat target instructions are to be executed for the second or later time, updates operands of the repeat target instructions for use in the second or later time execution, to the generated updated operands and outputs the updated operands.

Abstract: A header attaching unit attaches, for each destination of a plurality of packets, a number to each of the packets. The packets have a plurality of types. Furthermore, the header attaching unit sends the packets, to each of which the number is attached, via one of virtual channels in accordance with the types of the packets. Furthermore, an accumulation buffer receives packets sent from an arbitrating unit and accumulates the packets. An arbitrating unit and a management ID control unit determine, on the basis of the number, whether a specific type of packet is allowed to be output, decide the order the packets are output, and output the packets from the accumulation buffer.

Abstract: The presence of first storing unit that stores therein virtual bus data representing a virtual bus tree configuration in which some of the routes in the I/O bus system are virtually short-circuited; and a notifier that notifies the virtual bus data to a processing device disposed upstream of the I/O bus system makes it possible to operate the power source of the devices on the I/O bus system while the system is active.

Abstract: A composite sheet comprising at least one layer each of a substrate layer (layer A) made of a polystyrene resin and an ABS resin as the main components, a reinforcing layer (layer B) made of an ABS resin as the main component, and a surface layer (layer C) made of, as the main component, a polystyrene resin which contains a conductive filler, wherein the surface on at least one side is the above surface layer (layer C) is useful for a conductive composite sheet which has a small difference in physical properties between the machine and transverse directions and has high rigidity and folding endurance and which can easily be thermally formed into a tray or an embossed carrier tape.

Abstract: The present invention provides an asynchronous transmission device and asynchronous transmission method which reduce the synchronization processing overhead.