Patents by Inventor Masahiro Kuramoto

Masahiro Kuramoto has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10488685
    Abstract: A liquid crystal display device includes a thin film transistor substrate, a counter substrate that faces the thin film transistor substrate, a liquid crystal composition that is arranged between the thin film transistor substrate and the counter substrate, an oriented film that arranges orientation of the liquid crystal composition contacting with the thin film transistor substrate, a seal material that seals the liquid crystal composition between the two substrates, and a driver circuit. The driver circuit has a light transmission area that is formed inside of the driver circuit, and is higher in light transmittance than an area in which a non-transparent conductive film forming the driver circuit is formed, and a high sealing property area in which the seal material and an insulating film come into direct contact with each other between the light transmission area and an outer edge of the thin film transistor substrate.
    Type: Grant
    Filed: October 5, 2018
    Date of Patent: November 26, 2019
    Assignee: Japan Display Inc.
    Inventors: Takahiro Ochiai, Yuki Kuramoto, Masahiro Hoshiba
  • Publication number: 20190339970
    Abstract: A memory 11 stores therein first data and second data each of which has element data that forms a matrix. Arithmetic units 51 to 53 repeat, for each of a first predetermined row of the first data and a second predetermined row of the second data that are stored in the memory 11, by using the element data included in the first predetermined row and the element data included in the second predetermined row, a row portion operation based on the number of columns in the second data and performs, by using results of the row portion operations, an arithmetic operation process that acquires the operation results of the operation that uses the first data and the second data.
    Type: Application
    Filed: July 15, 2019
    Publication date: November 7, 2019
    Applicant: FUJITSU LIMITED
    Inventor: Masahiro Kuramoto
  • Patent number: 10452356
    Abstract: An arithmetic processing apparatus, includes: an arithmetic operation execution circuit configured to execute an arithmetic operation; a first register configured to store data to be used for an arithmetic operation by the arithmetic operation execution circuit; a first buffer configured to store data; a first controller configured to store, when an array of data is changed and the changed data is stored into the first register as the data to be used for the arithmetic operation, a plurality of data groups, which are successively received, into the first buffer; and a second controller configured to successively output, every time each of the plurality of data groups is stored into the first buffer, data included in the data groups stored in the first buffer to the first register.
    Type: Grant
    Filed: February 6, 2018
    Date of Patent: October 22, 2019
    Assignee: FUJITSU LIMITED
    Inventors: Junji Ichimiya, Masahiro Kuramoto
  • Patent number: 10353705
    Abstract: A memory 11 stores therein first data and second data each of which has element data that forms a matrix. Arithmetic units 51 to 53 repeat, for each of a first predetermined row of the first data and a second predetermined row of the second data that are stored in the memory 11, by using the element data included in the first predetermined row and the element data included in the second predetermined row, a row portion operation based on the number of columns in the second data and performs, by using results of the row portion operations, an arithmetic operation process that acquires the operation results of the operation that uses the first data and the second data.
    Type: Grant
    Filed: July 17, 2017
    Date of Patent: July 16, 2019
    Assignee: FUJITSU LIMITED
    Inventor: Masahiro Kuramoto
  • Publication number: 20190146802
    Abstract: An information processing apparatus includes a plurality of arithmetic processing apparatuses each of which is coupled to a first plurality of other arithmetic processing apparatuses among the plurality of arithmetic processing apparatuses via a first path and a second path, to a second plurality of other arithmetic processing apparatuses among the plurality of arithmetic processing apparatuses via a third path. Each of the plurality of arithmetic processing apparatuses includes first positional information on the first path, second positional information on the second path, and third positional information on the third path.
    Type: Application
    Filed: October 23, 2018
    Publication date: May 16, 2019
    Applicant: FUJITSU LIMITED
    Inventor: Masahiro Kuramoto
  • Patent number: 10248384
    Abstract: A plurality of floating-point registers store data therein. A processing execution unit executes arithmetic processing by using data stored in the floating-point registers. A first switch and a second switch select a route connecting the processing execution unit and the floating-point registers. A switch control unit controls the first switch and the second switch so as to switch a route to be selected, based on a switching instruction from the processing execution unit.
    Type: Grant
    Filed: June 9, 2017
    Date of Patent: April 2, 2019
    Assignee: FUJITSU LIMITED
    Inventors: Makoto Komagata, Takumi Maruyama, Shuji Yamamura, Masato Nakagawa, Masahiro Kuramoto
  • Publication number: 20190004795
    Abstract: An arithmetic processing device includes, a memory that stores a first data and a second data, a plurality of arithmetic circuits, a first memory arranged for each of the arithmetic circuits and that stores a first predetermined row having the predetermined number of the first data stored in the memory, a second memory arranged for each of the arithmetic circuits and that stores a second predetermined row having a predetermined number of the second data stored in the memory, and a plurality of multiply-add arithmetic circuits arranged for each of the arithmetic circuits, a number of the multiply-add arithmetic circuits corresponding to the predetermined number, each of the multiply-add arithmetic circuits that obtains a third data by executing the operation using the first data and the second data based on a result of performing a row operation which is an operation of one row of the first data.
    Type: Application
    Filed: June 22, 2018
    Publication date: January 3, 2019
    Applicant: FUJITSU LIMITED
    Inventor: Masahiro Kuramoto
  • Publication number: 20180232207
    Abstract: An arithmetic processing apparatus, includes: an arithmetic operation execution circuit configured to execute an arithmetic operation; a first register configured to store data to be used for an arithmetic operation by the arithmetic operation execution circuit; a first buffer configured to store data; a first controller configured to store, when an array of data is changed and the changed data is stored into the first register as the data to be used for the arithmetic operation, a plurality of data groups, which are successively received, into the first buffer; and a second controller configured to successively output, every time each of the plurality of data groups is stored into the first buffer, data included in the data groups stored in the first buffer to the first register.
    Type: Application
    Filed: February 6, 2018
    Publication date: August 16, 2018
    Applicant: FUJITSU LIMITED
    Inventors: Junji Ichimiya, Masahiro Kuramoto
  • Publication number: 20180181406
    Abstract: Each of product-sum arithmetic units 501 to 503 acquires, from a register file 410, different pieces of first element data included in a first predetermined row of first data that forms a matrix; acquires, from a register file 420, same pieces of second element data included in a second predetermined row of second data that forms a matrix; performs a row portion operation that is an operation performed on the first data by an amount corresponding to a single row by performing a process of performing an operation using the acquired first element data and the second element data; and performs an operation by using the first data and the second data based on the result of the row portion operation.
    Type: Application
    Filed: October 13, 2017
    Publication date: June 28, 2018
    Applicant: FUJITSU LIMITED
    Inventor: Masahiro Kuramoto
  • Publication number: 20180046458
    Abstract: A memory 11 stores therein first data and second data each of which has element data that forms a matrix. Arithmetic units 51 to 53 repeat, for each of a first predetermined row of the first data and a second predetermined row of the second data that are stored in the memory 11, by using the element data included in the first predetermined row and the element data included in the second predetermined row, a row portion operation based on the number of columns in the second data and performs, by using results of the row portion operations, an arithmetic operation process that acquires the operation results of the operation that uses the first data and the second data.
    Type: Application
    Filed: July 17, 2017
    Publication date: February 15, 2018
    Applicant: FUJITSU LIMITED
    Inventor: Masahiro Kuramoto
  • Publication number: 20180039480
    Abstract: A plurality of floating-point registers store data therein. A processing execution unit executes arithmetic processing by using data stored in the floating-point registers. A first switch and a second switch select a route connecting the processing execution unit and the floating-point registers. A switch control unit controls the first switch and the second switch so as to switch a route to be selected, based on a switching instruction from the processing execution unit.
    Type: Application
    Filed: June 9, 2017
    Publication date: February 8, 2018
    Inventors: MAKOTO KOMAGATA, Takumi Maruyama, Shuji Yamamura, Masato Nakagawa, Masahiro Kuramoto
  • Publication number: 20180004515
    Abstract: A processor includes: an address generating unit that, when an instruction decoded by a decoding unit is an instruction to execute arithmetic processing on a plurality of operand sets each including a plurality of operands that are objects of the arithmetic processing, in parallel a plurality of times, generates an address set corresponding to each of the operand sets of the arithmetic processing for each time, based on a certain address displacement with respect to the plurality of operands included in each of the operand sets; a plurality of instruction queues that hold the generated address sets corresponding to the respective operand sets, in correspondence to respective processing units; and a plurality of processing units that perform the arithmetic processing in parallel on the operand sets obtained based on the respective address sets outputted by the plurality of instruction queues.
    Type: Application
    Filed: May 26, 2017
    Publication date: January 4, 2018
    Applicant: FUJITSU LIMITED
    Inventors: Shuji Yamamura, Takumi Maruyama, Masato Nakagawa, Masahiro Kuramoto
  • Publication number: 20170371655
    Abstract: A processor includes: a storage unit that stores instructions; a counting unit that specifies an instruction to be decoded by a count value; a decoding unit that decodes an instruction; and a control unit that, when the decoded instruction is a repeat instruction, updates the count value of the counting unit so as to cause repeat target instructions in number corresponding to a designated number of instructions, out of instructions succeeding the repeat instruction, to be repeatedly executed a designated number of repetition times, and generates updated operands being operation objects of the repeat target instructions that are to be executed for the second or later time, and when the repeat target instructions are to be executed for the second or later time, updates operands of the repeat target instructions for use in the second or later time execution, to the generated updated operands and outputs the updated operands.
    Type: Application
    Filed: May 26, 2017
    Publication date: December 28, 2017
    Applicant: FUJITSU LIMITED
    Inventors: Masato Nakagawa, Takumi Maruyama, Shuji Yamamura, Masahiro Kuramoto
  • Publication number: 20140304450
    Abstract: A header attaching unit attaches, for each destination of a plurality of packets, a number to each of the packets. The packets have a plurality of types. Furthermore, the header attaching unit sends the packets, to each of which the number is attached, via one of virtual channels in accordance with the types of the packets. Furthermore, an accumulation buffer receives packets sent from an arbitrating unit and accumulates the packets. An arbitrating unit and a management ID control unit determine, on the basis of the number, whether a specific type of packet is allowed to be output, decide the order the packets are output, and output the packets from the accumulation buffer.
    Type: Application
    Filed: March 27, 2014
    Publication date: October 9, 2014
    Applicant: FUJITSU LIMITED
    Inventors: Koichi Maeda, Masahiro Kuramoto
  • Publication number: 20140289444
    Abstract: The presence of first storing unit that stores therein virtual bus data representing a virtual bus tree configuration in which some of the routes in the I/O bus system are virtually short-circuited; and a notifier that notifies the virtual bus data to a processing device disposed upstream of the I/O bus system makes it possible to operate the power source of the devices on the I/O bus system while the system is active.
    Type: Application
    Filed: January 10, 2014
    Publication date: September 25, 2014
    Applicant: FUJITSU LIMITED
    Inventor: Masahiro Kuramoto
  • Patent number: 7794807
    Abstract: A composite sheet comprising at least one layer each of a substrate layer (layer A) made of a polystyrene resin and an ABS resin as the main components, a reinforcing layer (layer B) made of an ABS resin as the main component, and a surface layer (layer C) made of, as the main component, a polystyrene resin which contains a conductive filler, wherein the surface on at least one side is the above surface layer (layer C) is useful for a conductive composite sheet which has a small difference in physical properties between the machine and transverse directions and has high rigidity and folding endurance and which can easily be thermally formed into a tray or an embossed carrier tape.
    Type: Grant
    Filed: September 5, 2005
    Date of Patent: September 14, 2010
    Assignee: Denki Kagaku Kogyo Kabushiki Kaisha
    Inventors: Takeshi Miyakawa, Yasushi Hirokawa, Masahiro Kuramoto
  • Patent number: 7602868
    Abstract: The present invention provides an asynchronous transmission device and asynchronous transmission method which reduce the synchronization processing overhead.
    Type: Grant
    Filed: January 30, 2006
    Date of Patent: October 13, 2009
    Assignee: Fujitsu Limited
    Inventors: Jun Tsuiki, Masao Koyabu, Masahiro Kuramoto, Junichi Inagaki
  • Patent number: 7555699
    Abstract: A method for address error check in a storage control circuit having a storage unit operable to store data in a storage area specified by an address encodes a first code assigned to the address with an even number of bits, encodes a second code assigned to the data written to the storage unit with an odd number of bits, generates a check code based on the first and second codes and stores the check code in the storage unit in correspondence with the data written to the storage unit, and conducts an error check based on data read from the storage unit, a check code corresponding to the data read, and a read address, thus detecting a multi-bit address error.
    Type: Grant
    Filed: September 28, 2005
    Date of Patent: June 30, 2009
    Assignee: Fujitsu Limited
    Inventors: Masahiro Kuramoto, Masao Koyabu, Jun Tsuiki, Junichi Inagaki
  • Patent number: 7509482
    Abstract: A memory device stores entries waiting to be processed. Row numbers of matrix information correspond to storage positions within the memory device, column numbers correspond to positions within the order of the entries, and every matrix element corresponding to the storage position and the position within the order of the entry stored in this storage position has a predetermined value. An operation between the first vector information indicating storage positions of processable entries and each column of the matrix information is performed and the second vector information indicating positions within the order of the processable entries is generated. Then, a position to be processed is selected from among the positions of processable entries indicated by the second vector information, an element having the predetermined value in the column corresponding to the selected position is obtained, and an entry in the storage position corresponding to the element is processed.
    Type: Grant
    Filed: June 16, 2006
    Date of Patent: March 24, 2009
    Assignee: Fujitsu Limited
    Inventors: Takuji Takahashi, Masahiro Kuramoto
  • Patent number: 7475170
    Abstract: The present invention is a data transfer device, which comprises an input/output reception buffer, an input/output transmission buffer, a write data buffer, a read data buffer, a control information table, a write data storing process section, a write data transmission section, a read data buffer storing process section, an input/output transmission buffer storing process section and a control section that executes an access control for controlling the access to the memory by the write data transmission section and the read data buffer storing process section based on a control information table; thereby, a configuration optimum for both protocols of the memory bus and the input/output bus is obtained and the out-of-order execution is also achievable.
    Type: Grant
    Filed: July 25, 2005
    Date of Patent: January 6, 2009
    Assignee: Fujitsu Limited
    Inventors: Junichi Inagaki, Masao Koyabu, Jun Tsuiki, Masahiro Kuramoto