Abstract: A continuously variable transmission includes: a first pulley and a second pulley each including a fixed pulley and a movable pulley; and an endless member wound around the first pulley and the second pulley, wherein the continuously variable transmission continuously changes a speed ratio by controlling a thrust of the movable pulley with a hydraulic pressure, the thrust of the movable pulley is made smaller as a rotation speed of the first pulley decreases, and when the rotation speed of the first pulley is lower than a predetermined rotation speed, the thrust of the movable pulley in a case where the speed ratio is on a Low side of the predetermined speed ratio is not made smaller than the thrust of the movable pulley in a case where the speed ratio is on a High side of the predetermined speed ratio.

Abstract: A memory controller for a computer system having a processor and dynamic random access memories (DRAMs) which are grouped into banks, and having multiple latches associated respectively with the groups of DRAMs. Each latch stores a row address from the processor in response to a row address strobe (RAS) signal when the corresponding memory bank is selected and one of the latches is selected corresponding to the selected memory bank. The row address stored in the selected latch is compared by a comparator with a row address from the processor. Initially, a controller accesses the DRAMs of a bank currently selected using a first row address from the processor. If the same row of the selected bank is addressed again, a coincidence is detected by the comparator, and in response, the controller accesses the DRAMs using the same row address and a column address from the processor.

Abstract: An object of the present invention is to reduce the number of external connection terminals of an LSI that are required for performing testing in an operating state. The test signal output circuit of the present invention comprises one or more test signal output terminals, one or more test mode signal input terminals, a decoder for interpreting signals from the test mode signal input terminals, and one or more selectors for selecting internal signals in response to the output of the decoder and outputting the selected signals from the respective test signal output terminal.

Abstract: A microprocessor having three kinds of bus cycle mode including a read cycle, a write cycle and an instruction fetch cycle, comprises a register having three bits corresponding to the read cycle, the write cycle and the instruction fetch cycle, respectively. A combinational circuit is connected to receive a code set in the register and coded information indicating the kind of bus cycle mode. An output circuit receiving an output of the combinational circuit operates to output the output of the combinational circuit in synchronism with a start of a corresponding bus cycle.

Abstract: A test signal output circuit comprising a decoder for decoding test-mode signals from test-mode signal input terminals, and selectors each for, in response to the output of this decoder, selecting specified ones of internal signals of the LSI, and outputting them at the test signal output terminals.In virtue of this, tests of the LSI in operation can be performed substantially without increasing the number of external connection terminals of LSI.

Abstract: An effective address pre-calculation type pipelined microprocessor comprises a register file which can be used for a base address for an operand address and an effective address calculation unit for calculating and generating an effective address of an operand prior to execution of an instruction, by using a register included in the register file as a base address register. A copy register is provided for selecting and holding either the calculated effective address or a modification amount added result obtained by adding a constant number to the calculated effective address, and a copy valid flag is provided for storing a history of a written condition of the copy register. When an auto-modification designation mode is detected, a calculated effective address or the modification amount added result is written to the copy register. A copy register identification code latch stores an identification code of a register which is used as a base address register in the auto-modification designation mode.

Abstract: An open type metal cord has a plurality of cord units each constituted by at least one preformed metal wire member. The wire members within a given cord unit have the same preforming ratio but have a different ratio from that of the wire members within another cord unit. A difference between the largest preforming ratio and the smallest preforming ratio in cord units falls within the range of 0.20 to 0.40. In this case, the maximum preforming ratio possible for the wire members is 1.65 and the minimum preforming ratio possible for the wire members is 1.05. A total number of wire members constituting a metal cord according to the present invention is 3 to 5.