Patents by Inventor Masahiro Matsuda

Masahiro Matsuda has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240134000
    Abstract: A radar system, a radar device, and an interference avoidance method are obtained that can utilize frequency effectively even in three or more radar devices. A radar system includes three or more radar devices and a schedule management controller. Schedule management controller predicts an interference time period that is a time period during which the overlapping scanning/radiation range is generated, determines a first interference avoidance measure that is a measure to cause radar devices to use respective different use frequencies while keeping a restriction on the number of frequency channels, in the predicted interference time period, and determines a second interference avoidance measure to be performed by a radar device that is unable to avoid interference by the first interference avoidance measure.
    Type: Application
    Filed: February 16, 2022
    Publication date: April 25, 2024
    Applicant: Mitsubishi Electric Corporation
    Inventors: Takamichi NAKAMIZO, Ikuya KAKIMOTO, Tomoya MATSUDA, Masahiro HAGIO
  • Publication number: 20240134238
    Abstract: A display panel includes a display region and a peripheral region other than the display region. The display panel includes, in the peripheral region, a gate drive circuit and a first trunk line extending in a column direction. The first trunk line includes a first edge on a first side corresponding to the display region side in the row direction and a second edge on a second side corresponding to a side opposite to the display region in the row direction. The first trunk line includes a first portion and a second portion, each including the first edge and the second edge, and the first edge of the second portion is closer to the second side in the row direction than the first edge of the first portion. The first portion is not provided with an element, and the second portion includes a region provided with an element.
    Type: Application
    Filed: September 26, 2023
    Publication date: April 25, 2024
    Inventors: Hidetoshi NAKAGAWA, Yoshihisa TAKAHASHI, Masahiro MATSUDA
  • Publication number: 20240136369
    Abstract: A display panel includes a display region defined by a plurality of pixels P and a peripheral region other than the display region. The display panel includes a gate drive circuit and a dummy capacitance portion in the peripheral region. The gate drive circuit includes a shift register. The dummy capacitance portion includes a plurality of capacitance elements connected in parallel and connected to a dummy stage. Each of the plurality of capacitance elements includes a first capacitance electrode, a second capacitance electrode, and a dielectric layer positioned between the first capacitance electrode and the second capacitance electrode. The dummy capacitance portion further includes at least one first connection portion with two ends respectively connected to the first capacitance electrode of any one of the plurality of capacitance elements and to the first capacitance electrode of any other one of the plurality of capacitance elements.
    Type: Application
    Filed: September 26, 2023
    Publication date: April 25, 2024
    Inventors: Hidetoshi NAKAGAWA, Yoshihisa TAKAHASHI, Masahiro MATSUDA
  • Publication number: 20240121912
    Abstract: A cold plate includes: a metal base plate having a first surface, a second surface on a side opposite the first surface, and fins disposed in parallel on the first surface; and a topped cylindrical resin cover covering the fins. The first surface has a recessed portion recessed toward the second surface. The topped cylindrical resin cover is heat-fused to the metal base plate on an inner surface of the recessed portion.
    Type: Application
    Filed: January 21, 2022
    Publication date: April 11, 2024
    Applicant: Fujikura Ltd.
    Inventors: Masahiro Matsuda, Koichi Mashiko, Yoji Kawahara
  • Publication number: 20240072636
    Abstract: Provided is a power conversion circuit, including: a first switching element and a second switching element connected in parallel to each other; and a control unit configured to control turn-on/off of each of the switching elements, wherein a current value at a cross point of current-voltage characteristics when a forward current flows through the first switching element and current-voltage characteristics when a current flows through the second switching element is greater than a rated current value of the power conversion circuit.
    Type: Application
    Filed: October 26, 2023
    Publication date: February 29, 2024
    Inventors: Masahiro SUGIMOTO, Shinpei MATSUDA
  • Publication number: 20220337430
    Abstract: An information processing device (10) detects an authentication status of a network authentication module (12) mounted on the information processing device (10) or a connection status of a network controlled according to the authentication status. Then, the information processing device (10) controls execution of an electronic signature according to signature information stored in the network authentication module (12) on the basis of the detected authentication status or connection status.
    Type: Application
    Filed: July 6, 2022
    Publication date: October 20, 2022
    Applicant: FUJITSU LIMITED
    Inventors: Kazuya UNO, Takayuki Hasebe, Masahiro MATSUDA, Tatsuro Matsumoto, Ryuichi TAKECHI
  • Publication number: 20220128323
    Abstract: A cold plate includes: a metal plate on which a plurality of fins are disposed; and a resin cover which covers the plurality of fins. A roughened portion is disposed on a tip surface of at least one of the plurality of fins. The roughened portion and the resin cover are fused to each other.
    Type: Application
    Filed: October 13, 2021
    Publication date: April 28, 2022
    Applicant: Fujikura Ltd.
    Inventors: Koichi Mashiko, Masahiro Matsuda
  • Patent number: 11289552
    Abstract: A display panel includes a substrate, a gate metal layer formed on a substrate, an insulating layer that covers the gate metal layer, and a source metal layer formed on the insulating layer. In a driving circuit region, the gate metal layer includes a first electrode and a second electrode separated from each other in a first direction and close to each other. The first electrode is positioned nearer than the second electrode to an active region and has a first side on a side facing the second electrode. The second electrode includes an ESD sacrificial portion. The ESD sacrificial portion includes a first part extending in the first direction and a second part facing the first side and extending in a second direction intersecting the first direction, the second part not overlapping a source metal of the source metal layer.
    Type: Grant
    Filed: February 25, 2021
    Date of Patent: March 29, 2022
    Assignee: SHARP KABUSHIKI KAISHA
    Inventors: Hidetoshi Nakagawa, Yoshihisa Takahashi, Masahiro Matsuda
  • Publication number: 20210272949
    Abstract: A display panel includes a substrate, a gate metal layer formed on a substrate, an insulating layer that covers the gate metal layer, and a source metal layer formed on the insulating layer. In a driving circuit region, the gate metal layer includes a first electrode and a second electrode separated from each other in a first direction and close to each other. The first electrode is positioned nearer than the second electrode to an active region and has a first side on a side facing the second electrode. The second electrode includes an ESD sacrificial portion. The ESD sacrificial portion includes a first part extending in the first direction and a second part facing the first side and extending in a second direction intersecting the first direction, the second part not overlapping a source metal of the source metal layer.
    Type: Application
    Filed: February 25, 2021
    Publication date: September 2, 2021
    Inventors: HIDETOSHI NAKAGAWA, YOSHIHISA TAKAHASHI, MASAHIRO MATSUDA
  • Patent number: 10359675
    Abstract: The liquid crystal display panel includes: storage capacitors respectively provided for a plurality of pixels on a substrate; a plurality of storage capacitor lines 37 arrayed in a column direction and each connected to corresponding ones of the storage capacitors, each storage capacitor line 37 belonging to one of N groups (where N is an integer equal to or greater than 2), such that every Nth storage capacitor line 37 belongs to an identical group; a plurality of branch lines 38 arrayed in a row direction, each branch line 38 being connected to more than one of the plurality of storage capacitor lines 37 that belong to an identical group; a plurality of trunk lines 71 to 82 at a column-direction edge of the substrate, each supplying an identical signal to a number of storage capacitor lines 37 that belong to one of the N groups via one or more of the plurality of branch lines 38; and a plurality of signal sending sections 7 each being coupled to associated trunk lines among the plurality of trunk lines 71 t
    Type: Grant
    Filed: September 11, 2017
    Date of Patent: July 23, 2019
    Assignee: Sakai Display Products Corporation
    Inventor: Masahiro Matsuda
  • Publication number: 20170371216
    Abstract: The liquid crystal display panel includes: storage capacitors respectively provided for a plurality of pixels on a substrate; a plurality of storage capacitor lines 37 arrayed in a column direction and each connected to corresponding ones of the storage capacitors, each storage capacitor line 37 belonging to one of N groups (where N is an integer equal to or greater than 2), such that every Nth storage capacitor line 37 belongs to an identical group; a plurality of branch lines 38 arrayed in a row direction, each branch line 38 being connected to more than one of the plurality of storage capacitor lines 37 that belong to an identical group; a plurality of trunk lines 71 to 82 at a column-direction edge of the substrate, each supplying an identical signal to a number of storage capacitor lines 37 that belong to one of the N groups via one or more of the plurality of branch lines 38; and a plurality of signal sending sections 7 each being coupled to associated trunk lines among the plurality of trunk lines 71 t
    Type: Application
    Filed: September 11, 2017
    Publication date: December 28, 2017
    Inventor: Masahiro Matsuda
  • Patent number: 9749944
    Abstract: A communication device includes a communication portion and a controller that determines whether or not a communication terminal from which the communication portion has received a connection request is a specified communication terminal. The controller makes a connection with the specified communication terminal based on the determination result of whether or not the communication terminal from which the communication portion has received the connection request is the specified communication terminal and transmits connection permission/refusal setting information to the specified communication terminal with which the controller has made a connection to allow a user to provide a connection permission/refusal setting of a communication terminal other than the specified communication terminal.
    Type: Grant
    Filed: April 17, 2015
    Date of Patent: August 29, 2017
    Assignee: Funai Electric Co., Ltd.
    Inventor: Masahiro Matsuda
  • Publication number: 20160350133
    Abstract: An information processing apparatus includes a processor configured to extract one or more processing codes describing a screen of the program by analyzing processing codes in a program, to generate a processing code group for screen processing by combining one or more extracted processing codes in a manner of being executable by an electronic equipment, to transmit the processing code group for the screen processing to the electronic equipment, to execute the processing codes excluding the processing code group for the screen processing in the program upon accepting a processing requests from the one or more extracted processing codes contained in the processing code group for the screen processing executed by the electronic equipment, and to transmit execution results of the processing codes, associated with the processing requests, in the program to the electronic equipment.
    Type: Application
    Filed: April 8, 2016
    Publication date: December 1, 2016
    Applicant: FUJITSU LIMITED
    Inventors: Tomoharu Imai, Koichi Yamasaki, Ryo Miyamoto, Kenichi Horio, Kazuki Matsui, Masahiro MATSUDA
  • Publication number: 20160290739
    Abstract: A vapor chamber is provided which includes a container including a first region which is heated and a second region which dissipates a heat and having a plate shape, and a working fluid which is encapsulated inside the container. The working fluid is evaporated by a heat transferred to a first region, after a vapor which is an evaporated working fluid flows to the second region, the heat is dissipated and the vapor is condensed, and the working fluid which is the condensed vapor is circulated to the first region.
    Type: Application
    Filed: March 28, 2016
    Publication date: October 6, 2016
    Applicant: FUJIKURA LTD.
    Inventors: Masataka MOCHIZUKI, Masahiro MATSUDA, Yuji SAITO, Masakazu OHASHI, Makoto TAKAHASHI, Akihiro TAKAMIYA, Guo ZHEN
  • Patent number: 9276019
    Abstract: A method of manufacturing an array substrate 20 according to the present invention includes a line forming step, and line forming step includes following performances. A plurality of source lines 27 are formed on a glass substrate GS so as to extend from a first region A1 on the glass substrate GS to a second region A2 that is adjacent to the first region on an outer side thereof. A plurality of source driver side check lines 45A are formed on the glass substrate GS so as to extend from the second region A2 to a third region that is adjacent to the first region A1 on an outer side thereof and adjacent to the second region A2. A plurality of first line connection portions 49 are formed in the second region A2 and the first line connection portions 49 connect the source lines 27 and the first source driver side check lines 45A. A capacity stem line 43 and a common line 44 are formed to extend from the first region A1 to the third region A3.
    Type: Grant
    Filed: July 12, 2012
    Date of Patent: March 1, 2016
    Assignee: SHARP KABUSHIKI KAISHA
    Inventors: Takaharu Yamada, Ryohki Itoh, Masahiro Yoshida, Hidetoshi Nakagawa, Takuya Ohishi, Masahiro Matsuda, Kazutoshi Kida
  • Patent number: D781211
    Type: Grant
    Filed: March 16, 2016
    Date of Patent: March 14, 2017
    Assignee: Nissan Motor Co., Ltd.
    Inventors: Atsushi Satou, Masahiro Matsuda
  • Patent number: D812536
    Type: Grant
    Filed: March 17, 2017
    Date of Patent: March 13, 2018
    Assignee: Nissan Motor Co., Ltd.
    Inventors: Masahiro Matsuda, Ken Okabe
  • Patent number: D853918
    Type: Grant
    Filed: March 16, 2016
    Date of Patent: July 16, 2019
    Assignee: Nissan Motor Co., Ltd.
    Inventors: Atsushi Satou, Masahiro Matsuda, Shigeyoshi Kabata, Sachiko Tanaka
  • Patent number: D917358
    Type: Grant
    Filed: October 11, 2019
    Date of Patent: April 27, 2021
    Assignee: Nissan Motor Co., Ltd.
    Inventors: Masahiro Matsuda, Daniel Schlapp
  • Patent number: D948399
    Type: Grant
    Filed: August 25, 2020
    Date of Patent: April 12, 2022
    Assignee: Nissan Motor Co., Ltd.
    Inventors: Yohei Noshiro, Masahiro Matsuda