Patents by Inventor Masahiro Moniwa
Masahiro Moniwa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 8652895Abstract: A memory cell of an SRAM has two drive MISFETs and two vertical MISFETs. The p channel vertical MISFETs are formed above the n channel drive MISFETs. The vertical MISFETs respectively mainly include a laminate formed of a lower semiconductor layer, intermediate semiconductor layer and upper semiconductor layer laminated in this sequence, a gate insulating film of silicon oxide formed on the surface of the side wall of the laminate, and a gate electrode formed so as to cover the side wall of the laminate. The vertical MISFETs are perfect depletion type MISFETs.Type: GrantFiled: July 5, 2011Date of Patent: February 18, 2014Assignee: Renesas Electronics CorporationInventors: Masahiro Moniwa, Hiraku Chakihara, Kousuke Okuyama, Yasuhiko Takahashi
-
Patent number: 8546783Abstract: A semiconductor device and a method of manufacturing the same with easy formation of a phase change film is realized, realizing high integration and using a phase change film as a memory element. Between a MISFET of a region forming one memory cell and an adjoining MISFET, each MISFET source adjoins in the front surface of an insulating semiconductor substrate. A multi-layer structure of a phase change film and electric conduction film of specific resistance lower than the specific resistance is formed in plan view of the front surface of a semiconductor substrate ranging over each source of both MISFETs, and a plug is stacked thereon. The multi-layer structure functions as a wiring extending and existing in parallel on the surface of the semiconductor substrate, and an electric conduction film sends current in a parallel direction on the surface of the semiconductor substrate.Type: GrantFiled: July 3, 2012Date of Patent: October 1, 2013Assignee: Renesas Electronics CorporationInventors: Masahiro Moniwa, Nozomu Matsuzaki, Riichiro Takemura
-
Patent number: 8476138Abstract: Vertical MISFETs are formed over drive MISFETs and transfer MISFETs. The vertical MISFETs comprise rectangular pillar laminated bodies each formed by laminating a lower semiconductor layer (drain), an intermediate semiconductor layer, and an upper semiconductor layer (source), and gate electrodes formed on corresponding side walls of the laminated bodies with gate insulating films interposed therebetween. In each vertical MISFET, the lower semiconductor layer constitutes a drain, the intermediate semiconductor layer constitutes a substrate (channel region), and the upper semiconductor layer constitutes a source. The lower semiconductor layer, the intermediate semiconductor layer and the upper semiconductor layer are each comprised of a silicon film. The lower semiconductor layer and the upper semiconductor layer are doped with a p type and constituted of a p type silicon film.Type: GrantFiled: June 1, 2011Date of Patent: July 2, 2013Assignees: Hitachi ULSI Systems Co., Ltd., Renesas Electronics CorporationInventors: Hiraku Chakihara, Kousuke Okuyama, Masahiro Moniwa, Makoto Mizuno, Keiji Okamoto, Mitsuhiro Noguchi, Tadanori Yoshida, Yasuhiko Takahshi, Akio Nishida
-
Patent number: 8420527Abstract: Interconnections are formed over an interlayer insulating film which covers MISFETQ1 formed on the principal surface of a semiconductor substrate, while dummy interconnections are disposed in a region spaced from such interconnections. Dummy interconnections are disposed also in a scribing area. Dummy interconnections are not formed at the peripheries of a bonding pad and a marker. In addition, a gate electrode of a MISFET and a dummy gate interconnection formed of the same layer are disposed. Furthermore, dummy regions are disposed in a shallow trench element-isolation region. After such dummy members are disposed, an insulating film is planarized by the CMP method.Type: GrantFiled: August 3, 2011Date of Patent: April 16, 2013Assignee: Renesas Electronics CorporationInventors: Yasushi Koubuchi, Koichi Nagasawa, Masahiro Moniwa, Youhei Yamada, Toshifumi Takeda
-
Patent number: 8338817Abstract: Any of a plurality of contact plugs which reaches a diffusion layer serving as a drain layer of an MOS transistor has an end provided in contact with a lower surface of a thin insulating film provided selectively on an interlayer insulating film. A phase change film constituted by GST to be a chalcogenide compound based phase change material is provided on the thin insulating film, and an upper electrode is provided thereon. Any of the plurality of contact plugs which reaches the diffusion layer serving as a source layer has an end connected directly to an end of a contact plug penetrating an interlayer insulating film.Type: GrantFiled: October 21, 2011Date of Patent: December 25, 2012Assignee: Renesas Electronics CorporationInventors: Masahiro Moniwa, Fumihiko Nitta, Masamichi Matsuoka, Satoshi Iida
-
Publication number: 20120286225Abstract: A semiconductor device and a method of manufacturing the same with easy formation of a phase change film is realized, realizing high integration and using a phase change film as a memory element. Between a MISFET of a region forming one memory cell and an adjoining MISFET, each MISFET source adjoins in the front surface of an insulating semiconductor substrate. A multi-layer structure of a phase change film and electric conduction film of specific resistance lower than the specific resistance is formed in plan view of the front surface of a semiconductor substrate ranging over each source of both MISFETs, and a plug is stacked thereon. The multi-layer structure functions as a wiring extending and existing in parallel on the surface of the semiconductor substrate, and an electric conduction film sends current in a parallel direction on the surface of the semiconductor substrate.Type: ApplicationFiled: July 3, 2012Publication date: November 15, 2012Applicant: Renesas Electronics CorporationInventors: Masahiro Moniwa, Nozomu Matsuzaki, Riichiro Takemura
-
Patent number: 8232543Abstract: A semiconductor device and a method of manufacturing the same with easy formation of a phase change film is realized, realizing high integration at the time of using a phase change film as a memory element. Between MISFET of the region which forms one memory cell, and MISFET which adjoined it, each source of MISFET adjoins in the front surface of a semiconductor substrate, insulating. And the multi-layer structure of a phase change film, and the electric conduction film of specific resistance lower than the specific resistance is formed in the plan view of the front surface of a semiconductor substrate ranging over each source of both MISFET, and a plug and a plug stacked on it. The multi-layer structure functions as a wiring extending and existing in parallel on the surface of a semiconductor substrate, and an electric conduction film sends the current of a parallel direction on the surface of a semiconductor substrate.Type: GrantFiled: January 10, 2011Date of Patent: July 31, 2012Assignee: Renesas Electronics CorporationInventors: Masahiro Moniwa, Nozomu Matsuzaki, Riichiro Takemura
-
Publication number: 20120037874Abstract: Any of a plurality of contact plugs which reaches a diffusion layer serving as a drain layer of an MOS transistor has an end provided in contact with a lower surface of a thin insulating film provided selectively on an interlayer insulating film. A phase change film constituted by GST to be a chalcogenide compound based phase change material is provided on the thin insulating film, and an upper electrode is provided thereon. Any of the plurality of contact plugs which reaches the diffusion layer serving as a source layer has an end connected directly to an end of a contact plug penetrating an interlayer insulating film.Type: ApplicationFiled: October 21, 2011Publication date: February 16, 2012Applicant: Renesas Electronics CorporationInventors: Masahiro MONIWA, Fumihiko NITTA, Masamichi MATSUOKA, Satoshi IIDA
-
Patent number: 8071456Abstract: Any of a plurality of contact plugs which reaches a diffusion layer serving as a drain layer of an MOS transistor has an end provided in contact with a lower surface of a thin insulating film provided selectively on an interlayer insulating film. A phase change film constituted by GST to be a chalcogenide compound based phase change material is provided on the thin insulating film, and an upper electrode is provided thereon. Any of the plurality of contact plugs which reaches the diffusion layer serving as a source layer has an end connected directly to an end of a contact plug penetrating an interlayer insulating film.Type: GrantFiled: August 27, 2010Date of Patent: December 6, 2011Assignee: Renesas Electronics CorporationInventors: Masahiro Moniwa, Fumihiko Nitta, Masamichi Matsuoka, Satoshi Iida
-
Publication number: 20110287595Abstract: Interconnections are formed over an interlayer insulating film which covers MISFETQ1 formed on the principal surface of a semiconductor substrate, while dummy interconnections are disposed in a region spaced from such interconnections. Dummy interconnections are disposed also in a scribing area. Dummy interconnections are not formed at the peripheries of a bonding pad and a marker. In addition, a gate electrode of a MISFET and a dummy gate interconnection formed of the same layer are disposed. Furthermore, dummy regions are disposed in a shallow trench element-isolation region. After such dummy members are disposed, an insulating film is planarized by the CMP method.Type: ApplicationFiled: August 3, 2011Publication date: November 24, 2011Inventors: Yasushi Koubuchi, Koichi Nagasawa, Masahiro Moniwa, Youhei Yamada, Toshifumi Takeda
-
Publication number: 20110275207Abstract: A memory cell of an SRAM has two drive MISFETs and two vertical MISFETs. The p channel vertical MISFETs are formed above the n channel drive MISFETs. The vertical MISFETs respectively mainly include a laminate formed of a lower semiconductor layer, intermediate semiconductor layer and upper semiconductor layer laminated in this sequence, a gate insulating film of silicon oxide formed on the surface of the side wall of the laminate, and a gate electrode formed so as to cover the side wall of the laminate. The vertical MISFETs are perfect depletion type MISFETs.Type: ApplicationFiled: July 5, 2011Publication date: November 10, 2011Inventors: Masahiro MONIWA, Hiraku Chakihara, Kousuke Okuyama, Yasuhiko Takahashi
-
Publication number: 20110230041Abstract: Vertical MISFETs are formed over drive MISFETs and transfer MISFETs. The vertical MISFETs comprise rectangular pillar laminated bodies each formed by laminating a lower semiconductor layer (drain), an intermediate semiconductor layer, and an upper semiconductor layer (source), and gate electrodes formed on corresponding side walls of the laminated bodies with gate insulating films interposed therebetween. In each vertical MISFET, the lower semiconductor layer constitutes a drain, the intermediate semiconductor layer constitutes a substrate (channel region), and the upper semiconductor layer constitutes a source. The lower semiconductor layer, the intermediate semiconductor layer and the upper semiconductor layer are each comprised of a silicon film. The lower semiconductor layer and the upper semiconductor layer are doped with a p type and constituted of a p type silicon film.Type: ApplicationFiled: June 1, 2011Publication date: September 22, 2011Inventors: Hiraku CHAKIHARA, Kousuke Okuyama, Masahiro Moniwa, Makoto Mizuno, Keiji Okamoto, Mitsuhiro Noguchi, Tadanori Yoshida, Yasuhiko Takahshi, Akio Nishida
-
Patent number: 8022550Abstract: Interconnections are formed over an interlayer insulating film which covers MISFETQ1 formed on the principal surface of a semiconductor substrate, while dummy interconnections are disposed in a region spaced from such interconnections. Dummy interconnections are disposed also in a scribing area. Dummy interconnections are not formed at the peripheries of a bonding pad and a marker. In addition, a gate electrode of a MISFET and a dummy gate interconnection formed of the same layer are disposed. Furthermore, dummy regions are disposed in a shallow trench element-isolation region. After such dummy members are disposed, an insulating film is planarized by the CMP method.Type: GrantFiled: December 30, 2009Date of Patent: September 20, 2011Assignee: Renesas Electronics CorporationInventors: Yasushi Koubuchi, Koichi Nagasawa, Masahiro Moniwa, Youhei Yamada, Toshifumi Takeda
-
Patent number: 7981738Abstract: A memory cell of an SRAM has two drive MISFETs and two vertical MISFETs. The p channel vertical MISFETs are formed above the n channel drive MISFETs. The vertical MISFETs respectively mainly include a laminate formed of a lower semiconductor layer, intermediate semiconductor layer and upper semiconductor layer laminated in this sequence, a gate insulating film of silicon oxide formed on the surface of the side wall of the laminate, and a gate electrode formed so as to cover the side wall of the laminate. The vertical MISFETs are perfect depletion type MISFETs.Type: GrantFiled: October 22, 2010Date of Patent: July 19, 2011Assignee: Renesas Electronics CorporationInventors: Masahiro Moniwa, Hiraku Chakihara, Kousuke Okuyama, Yasuhiko Takahashi
-
Patent number: 7972920Abstract: Vertical MISFETs are formed over drive MISFETs and transfer MISFETs. The vertical MISFETs comprise rectangular pillar laminated bodies each formed by laminating a lower semiconductor layer (drain), an intermediate semiconductor layer, and an upper semiconductor layer (source), and gate electrodes formed on corresponding side walls of the laminated bodies with gate insulating films interposed therebetween. In each vertical MISFET, the lower semiconductor layer constitutes a drain, the intermediate semiconductor layer constitutes a substrate (channel region), and the upper semiconductor layer constitutes a source. The lower semiconductor layer, the intermediate semiconductor layer and the upper semiconductor layer are each comprised of a silicon film. The lower semiconductor layer and the upper semiconductor layer are doped with a p type and constituted of a p type silicon film.Type: GrantFiled: February 4, 2010Date of Patent: July 5, 2011Assignees: Hitachi ULSI Systems Co., Ltd., Renesas Electronics Corp.Inventors: Hiraku Chakihara, Kousuke Okuyama, Masahiro Moniwa, Makoto Mizuno, Keiji Okamoto, Mitsuhiro Noguchi, Tadanori Yoshida, Yasuhiko Takahshi, Akio Nishida
-
Publication number: 20110101297Abstract: A semiconductor device and a method of manufacturing the same with easy formation of a phase change film is realized, realizing high integration at the time of using a phase change film as a memory element. Between MISFET of the region which forms one memory cell, and MISFET which adjoined it, each source of MISFET adjoins in the front surface of a semiconductor substrate, insulating. And the multi-layer structure of a phase change film, and the electric conduction film of specific resistance lower than the specific resistance is formed in the plan view of the front surface of a semiconductor substrate ranging over each source of both MISFET, and a plug and a plug stacked on it. The multi-layer structure functions as a wiring extending and existing in parallel on the surface of a semiconductor substrate, and an electric conduction film sends the current of a parallel direction on the surface of a semiconductor substrate.Type: ApplicationFiled: January 10, 2011Publication date: May 5, 2011Applicant: Renesas Electronics CorporationInventors: Masahiro MONIWA, Nozomu Matsuzaki, Riichiro Takemura
-
Patent number: 7902539Abstract: Any of a plurality of contact plugs which reaches a diffusion layer serving as a drain layer of an MOS transistor has an end provided in contact with a lower surface of a thin insulating film provided selectively on an interlayer insulating film. A phase change film constituted by GST to be a chalcogenide compound based phase change material is provided on the thin insulating film, and an upper electrode is provided thereon. Any of the plurality of contact plugs which reaches the diffusion layer serving as a source layer has an end connected directly to an end of a contact plug penetrating an interlayer insulating film.Type: GrantFiled: November 20, 2008Date of Patent: March 8, 2011Assignee: Renesas Technology Corp.Inventors: Masahiro Moniwa, Fumihiko Nitta, Masamichi Matsuoka, Satoshi Iida
-
Publication number: 20110034017Abstract: A memory cell of an SRAM has two drive MISFETs and two vertical MISFETs. The p channel vertical MISFETs are formed above the n channel drive MISFETs. The vertical MISFETs respectively mainly include a laminate formed of a lower semiconductor layer, intermediate semiconductor layer and upper semiconductor layer laminated in this sequence, a gate insulating film of silicon oxide formed on the surface of the side wall of the laminate, and a gate electrode formed so as to cover the side wall of the laminate. The vertical MISFETs are perfect depletion type MISFETs.Type: ApplicationFiled: October 22, 2010Publication date: February 10, 2011Inventors: Masahiro MONIWA, Hiraku Chakihara, Kousuke Okuyama, Yasuhiko Takahashi
-
Patent number: 7884348Abstract: A semiconductor device and a method of manufacturing the same with easy formation of a phase change film is realized, realizing high integration at the time of using a phase change film as a memory element. Between MISFET of the region which forms one memory cell, and MISFET which adjoined it, each source of MISFET adjoins in the front surface of a semiconductor substrate, insulating. And the multi-layer structure of a phase change film, and the electric conduction film of specific resistance lower than the specific resistance is formed in the plan view of the front surface of a semiconductor substrate ranging over each source of both MISFET, and a plug and a plug stacked on it. The multi-layer structure functions as a wiring extending and existing in parallel on the surface of a semiconductor substrate, and an electric conduction film sends the current of a parallel direction on the surface of a semiconductor substrate.Type: GrantFiled: April 5, 2010Date of Patent: February 8, 2011Assignee: Renesas Electronics CorporationInventors: Masahiro Moniwa, Nozomu Matsuzaki, Riichiro Takemura
-
Publication number: 20100323491Abstract: Any of a plurality of contact plugs which reaches a diffusion layer serving as a drain layer of an MOS transistor has an end provided in contact with a lower surface of a thin insulating film provided selectively on an interlayer insulating film. A phase change film constituted by GST to be a chalcogenide compound based phase change material is provided on the thin insulating film, and an upper electrode is provided thereon. Any of the plurality of contact plugs which reaches the diffusion layer serving as a source layer has an end connected directly to an end of a contact plug penetrating an interlayer insulating film.Type: ApplicationFiled: August 27, 2010Publication date: December 23, 2010Applicant: Renesas Technology Corp.Inventors: Masahiro MONIWA, Fumihiko Nitta, Masamichi Matsuoka, Satoshi Iida