Patents by Inventor Masahiro Nakayama

Masahiro Nakayama has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12235696
    Abstract: [Object] To provide an information processing apparatus, an information processing method, and a program that are capable of improving the convenience of the communication connection to an external apparatus. [Solution] An information processing apparatus including: a control unit configured to detect an external apparatus in a wireless communication scheme, and perform control such that power ON request data is transmitted to the external apparatus in accordance with a detection result within a certain time from a detection processing start for the external apparatus, the power ON request data requesting the external apparatus to be powered on.
    Type: Grant
    Filed: July 14, 2022
    Date of Patent: February 25, 2025
    Assignee: Sony Group Corporation
    Inventors: Masahiro Shimizu, Daisuke Nakayama, Yusuke Fujimoto, Masahiro Watanabe, Tetsunori Nakayama
  • Patent number: 11999308
    Abstract: An impact energy absorbing member includes an energy absorbing portion and an attachment portion. The attachment portion is fastened to the bumper reinforcement using a fastener, the fastener extending through the attachment portion and a wall of the bumper reinforcement and including an axis that extends in a direction intersecting an axial direction of the energy absorbing portion. The attachment portion and the energy absorbing portion are in a positional relationship in which the energy absorbing portion does not overlap the fastener when the impact energy absorbing member is viewed in a direction from the bumper reinforcement toward the energy absorbing portion in a vehicle front-rear direction.
    Type: Grant
    Filed: April 1, 2020
    Date of Patent: June 4, 2024
    Assignees: KABUSHIKI KAISHA TOYOTA JIDOSHOKKI, TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventors: Takuma Inoue, Shin Terada, Kazuyoshi Ogata, Masahiko Yasue, Kohei Mori, Masahiro Nakayama, Ryuta Kamiya
  • Publication number: 20220161747
    Abstract: An impact energy absorbing member includes an energy absorbing portion and an attachment portion. The attachment portion is fastened to the bumper reinforcement using a fastener, the fastener extending through the attachment portion and a wall of the bumper reinforcement and including an axis that extends in a direction intersecting an axial direction of the energy absorbing portion. The attachment portion and the energy absorbing portion are in a positional relationship in which the energy absorbing portion does not overlap the fastener when the impact energy absorbing member is viewed in a direction from the bumper reinforcement toward the energy absorbing portion in a vehicle front-rear direction.
    Type: Application
    Filed: April 1, 2020
    Publication date: May 26, 2022
    Applicants: KABUSHIKI KAISHA TOYOTA JIDOSHOKKI, TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventors: Takuma INOUE, Shin TERADA, Kazuyoshi OGATA, Masahiko YASUE, Kohei MORI, Masahiro NAKAYAMA, Ryuta KAMIYA
  • Patent number: 11294746
    Abstract: A non-transitory computer-readable storage medium storing a program that causes a computer to execute a process, the process includes determining whether an error log is included in an operation log over a terminal; when the error log is included in the operation log, specifying a start timing and a stop timing of a script including the error log stored in a memory based on the operation log; and extracting moving image data output to the terminal during execution of the script based on time information related to the specified start timing and stop timing of the script.
    Type: Grant
    Filed: September 21, 2020
    Date of Patent: April 5, 2022
    Assignee: FUJITSU LIMITED
    Inventors: Toshiyuki Fujishima, Susumu Koga, Masahiro Nakayama, Tomoyuki Kobayashi
  • Publication number: 20210096940
    Abstract: A non-transitory computer-readable storage medium storing a program that causes a computer to execute a process, the process includes determining whether an error log is included in an operation log over a terminal; when the error log is included in the operation log, specifying a start timing and a stop timing of a script including the error log stored in a memory based on the operation log; and extracting moving image data output to the terminal during execution of the script based on time information related to the specified start timing and stop timing of the script.
    Type: Application
    Filed: September 21, 2020
    Publication date: April 1, 2021
    Applicant: FUJITSU LIMITED
    Inventors: Toshiyuki Fujishima, Susumu Koga, Masahiro Nakayama, Tomoyuki Kobayashi
  • Publication number: 20150379379
    Abstract: A printer includes a storage unit that spools print jobs, a print job sorting unit that sorts the spooled print jobs into a processing order, and a printing unit that performs printing on a paper roll in response to the print jobs in the sorted processing order. The print job sorting unit sorts the print jobs into a processing order based on medium attributes of the paper roll supplied to the printing unit and medium attributes which are requested in the print job.
    Type: Application
    Filed: June 15, 2015
    Publication date: December 31, 2015
    Inventors: Hiroaki Kubota, Masahiro Nakayama
  • Publication number: 20150170928
    Abstract: A fabrication method of a silicon carbide substrate includes the following steps. By slicing a silicon carbide ingot, a first intermediate substrate having a first main surface and second main surface opposite to each other and a first SORI value, is formed. By etching at least one of the first main surface and the second main surface of the first intermediate substrate, a second intermediate substrate having a second SORI value smaller than the first SORI value is formed. By grinding at least one of the first main surface and the second main surface of the second intermediate substrate, a third intermediate substrate having a third SORI value greater than the second SORI value is formed. Accordingly, a silicon carbide substrate with small warpage is provided.
    Type: Application
    Filed: December 16, 2013
    Publication date: June 18, 2015
    Applicant: SUMITOMO ELECTRIC INDUSTRIES, LTD.
    Inventor: Masahiro NAKAYAMA
  • Publication number: 20150135517
    Abstract: The present invention provides a degradation diagnosis device for a cell, the degradation diagnosis device for a cell comparing a potential variation characteristic of a comparison subject cell during discharging and after discharging is stopped and a potential variation characteristic of a degradation diagnosis subject cell during discharging and after discharging is stopped, in a case where the potential variation characteristic of the comparison subject cell during discharging and after discharging is stopped and the potential variation characteristic of the degradation diagnosis subject cell during discharging and after discharging is stopped are not same, diagnosing a cause of the degradation as including degradation of an active material, and in a case where they are same, diagnosing the cause of the degradation as being other than the active material.
    Type: Application
    Filed: June 1, 2012
    Publication date: May 21, 2015
    Applicant: TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventors: Takayoshi Doi, Masahiro Nakayama, Satoshi Yoshida, Yuzo Miura
  • Patent number: 8723219
    Abstract: Technology of making freestanding gallium nitride (GaN) wafers has been matured at length. Gallium nitride is rigid but fragile. Chamfering of a periphery of a GaN wafer is difficult. At present edges are chamfered by a rotary whetstone of gross granules with weak pressure. Minimum roughness of the chamfered edges is still about Ra 10 ?m to Ra 6 ?m. The large edge roughness causes scratches, cracks, splits or breaks in transferring process or wafer process. A wafer of the present invention is bevelled by fixing the wafer to a chuck of a rotor, bringing an edge of the wafer into contact with an elastic whetting material having a soft matrix and granules implanted on the soft matrix, rotating the wafer and feeding the whetting material. Favorably, several times of chamfering edges by changing the whetting materials of smaller granules are given to the wafer. The chamfering can realize small roughness of Ra10 nm and Ra5 ?m at edges of wafers.
    Type: Grant
    Filed: July 8, 2013
    Date of Patent: May 13, 2014
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Masahiro Nakayama, Masato Irikura
  • Publication number: 20130292696
    Abstract: Technology of making freestanding gallium nitride (GaN) wafers has been matured at length. Gallium nitride is rigid but fragile. Chamfering of a periphery of a GaN wafer is difficult. At present edges are chamfered by a rotary whetstone of gross granules with weak pressure. Minimum roughness of the chamfered edges is still about Ra 10 ?m to Ra 6 ?m. The large edge roughness causes scratches, cracks, splits or breaks in transferring process or wafer process. A wafer of the present invention is bevelled by fixing the wafer to a chuck of a rotor, bringing an edge of the wafer into contact with an elastic whetting material having a soft matrix and granules implanted on the soft matrix, rotating the wafer and feeding the whetting material. Favorably, several times of chamfering edges by changing the whetting materials of smaller granules are given to the wafer. The chamfering can realize small roughness of Ra10 nm and Ra5 ?m at edges of wafers.
    Type: Application
    Filed: July 8, 2013
    Publication date: November 7, 2013
    Inventors: MASAHIRO NAKAYAMA, MASATO IRIKURA
  • Patent number: 8482032
    Abstract: Technology of making freestanding gallium nitride (GaN) wafers has been matured at length. Gallium nitride is rigid but fragile. Chamfering of a periphery of a GaN wafer is difficult. At present edges are chamfered by a rotary whetstone of gross granules with weak pressure. Minimum roughness of the chamfered edges is still about Ra 10 ?m to Ra 6 ?m. The large edge roughness causes scratches, cracks, splits or breaks in transferring process or wafer process. A wafer of the present invention is bevelled by fixing the wafer to a chuck of a rotor, bringing an edge of the wafer into contact with an elastic whetting material having a soft matrix and granules implanted on the soft matrix, rotating the wafer and feeding the whetting material. Favorably, several times of chamfering edges by changing the whetting materials of smaller granules are given to the wafer. The chamfering can realize small roughness of Ra 10 nm and Ra 5 ?m at edges of wafers.
    Type: Grant
    Filed: August 17, 2011
    Date of Patent: July 9, 2013
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Masahiro Nakayama, Masato Irikura
  • Publication number: 20120135549
    Abstract: Polishing a nitride semiconductor monocrystalline wafer leaves it with a process-transformed layer. The process-transformed layer has to be etched to be removed. The chemical inertness of nitride semiconductor materials has, however, precluded suitable etching. Although potassium hydroxide, for example, or sulfuric acid have been proposed as GaN etchants, their ability to corrosively remove material from the Ga face is weak. Dry etching utilizing a halogen plasma is carried out in order to remove the process-transformed layer. The Ga face can be etched off with the halogen plasma. Nevertheless, owing to the dry etching, a problem arises again—surface contamination due to metal particles. To address the problem, wet etching with, as the etchant, solutions such as HF+H2O2, H2SO4+H2O2, HCl+H2O2, or HNO3, which are nonselective for Ga/N faces, have metal etching capability, and have an oxidation-reduction potential of 1.2 V or more, is performed.
    Type: Application
    Filed: February 6, 2012
    Publication date: May 31, 2012
    Applicant: SUMITOMO ELECTRIC INDUSTRIES, LTD.
    Inventors: Masahiro Nakayama, Naoki Matsumoto
  • Patent number: 8156999
    Abstract: This invention relates to an air conditioner having an air inlet at its upper portion. The heat exchanger (4) includes multiple plate fins (1) arranged in parallel so that air flows therebetween, and heat transfer tubes (2) perpendicularly inserted into the plate fins (1) and arranged perpendicularly to the air flow direction through which working fluid passes. The heat exchanger (4) includes a lower front heat exchanger (4a), an upper front heat exchanger (4b), and a rear heat exchanger (4c) separately produced and arranged to surround the circulating fan (5). The air pressure loss of the lower front heat exchanger (4a) is set to be smaller than the air pressure losses of the other heat exchangers.
    Type: Grant
    Filed: March 4, 2005
    Date of Patent: April 17, 2012
    Assignee: Mitsubisih Denki Kabushiki Kaisha
    Inventors: Akira Ishibashi, Hiroki Okazawa, Masahiro Nakayama, Tadashi Saitou
  • Patent number: 8133815
    Abstract: Compound-semiconductor-substrate polishing methods, compound semiconductor substrates, compound-semiconductor-epitaxial-substrate manufacturing methods, and compound semiconductor epitaxial substrates whereby oxygen superficially present on the substrates reduced. A compound semiconductor-substrate polishing method includes a preparation step (S10), a first polishing step (S20), and a second polishing step (S30). In the preparation step (S10), a compound semiconductor substrate is prepared. In the first polishing step (S20), the compound semiconductor substrate is polished with a chloric polishing agent. In the second polishing step (S30), subsequent to the first polishing step (S20), a polishing operation utilizing an alkaline aqueous solution containing an inorganic builder and having pH of 8.5 to 13.0 inclusive is performed.
    Type: Grant
    Filed: September 28, 2007
    Date of Patent: March 13, 2012
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Yoshio Mezaki, Takayuki Nishiura, Masahiro Nakayama
  • Publication number: 20110297959
    Abstract: Technology of making freestanding gallium nitride (GaN) wafers has been matured at length. Gallium nitride is rigid but fragile. Chamfering of a periphery of a GaN wafer is difficult. At present edges are chamfered by a rotary whetstone of gross granules with weak pressure. Minimum roughness of the chamfered edges is still about Ra 10 ?m to Ra 6 ?m. The large edge roughness causes scratches, cracks, splits or breaks in transferring process or wafer process. A wafer of the present invention is bevelled by fixing the wafer to a chuck of a rotor, bringing an edge of the wafer into contact with an elastic whetting material having a soft matrix and granules implanted on the soft matrix, rotating the wafer and feeding the whetting material. Favorably, several times of chamfering edges by changing the whetting materials of smaller granules are given to the wafer. The chamfering can realize small roughness of Ra 10 nm and Ra 5 ?m at edges of wafers.
    Type: Application
    Filed: August 17, 2011
    Publication date: December 8, 2011
    Applicant: Sumitomo Electric Industries, Ltd.
    Inventors: Masahiro NAKAYAMA, Masato Irikura
  • Patent number: 8022438
    Abstract: Technology of making freestanding gallium nitride (GaN) wafers has been matured at length. Gallium nitride is rigid but fragile. Chamfering of a periphery of a GaN wafer is difficult. At present edges are chamfered by a rotary whetstone of gross granules with weak pressure. Minimum roughness of the chamfered edges is still about Ra 10 ?m to Ra 6 ?m. The large edge roughness causes scratches, cracks, splits or breaks in transferring process or wafer process. A wafer of the present invention is bevelled by fixing the wafer to a chuck of a rotor, bringing an edge of the wafer into contact with an elastic whetting material having a soft matrix and granules implanted on the soft matrix, rotating the wafer and feeding the whetting material. Favorably, several times of chamfering edges by changing the whetting materials of smaller granules are given to the wafer. The chamfering can realize small roughness of Ra 10 nm and Ra 5 ?m at edges of wafers.
    Type: Grant
    Filed: May 6, 2009
    Date of Patent: September 20, 2011
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Masahiro Nakayama, Masato Irikura
  • Patent number: 8008165
    Abstract: Nitride semiconductor wafers which are produced by epitaxially grown nitride films on a foreign undersubstrate in vapor phase have strong inner stress due to misfit between the nitride and the undersubstrate material. A GaN wafer which has made by piling GaN films upon a GaAs undersubstrate in vapor phase and eliminating the GaAs undersubstrate bends upward due to the inner stress owing to the misfit of lattice constants between GaN and GaAs.
    Type: Grant
    Filed: July 14, 2010
    Date of Patent: August 30, 2011
    Assignees: Sumitomo Electric Industries, Ltd., Sony Corporation
    Inventors: Masahiro Nakayama, Naoki Matsumoto, Koshi Tamamura, Masao Ikeda
  • Publication number: 20100279440
    Abstract: Nitride semiconductor wafers which are produced by epitaxially grown nitride films on a foreign undersubstrate in vapor phase have strong inner stress due to misfit between the nitride and the undersubstrate material. A GaN wafer which has made by piling GaN films upon a GaAs undersubstrate in vapor phase and eliminating the GaAs undersubstrate bends upward due to the inner stress owing to the misfit of lattice constants between GaN and GaAs. Ordinary one-surface polishing having the steps of gluing a wafer with a surface on a flat disc, bringing another surface in contact with a lower turntable, pressing the disc, rotating the disc, revolving the turntable and whetting the lower surface, cannot remedy the inherent distortion. The Distortion worsens morphology of epitaxial wafers, lowers yield of via-mask exposure and invites cracks on surfaces. Nitride crystals are rigid but fragile. Chemical/mechanical polishing has been requested in vain.
    Type: Application
    Filed: July 14, 2010
    Publication date: November 4, 2010
    Applicants: SUMITOMO ELECTRIC INDUSTRIES, LTD., SONY CORPORATION
    Inventors: Masahiro NAKAYAMA, Naoki MATSUMOTO, Koshi TAMAMURA, Masao IKEDA
  • Patent number: 7786488
    Abstract: Nitride semiconductor wafers which are produced by epitaxially grown nitride films on a foreign undersubstrate in vapor phase have strong inner stress due to misfit between the nitride and the undersubstrate material. A GaN wafer which has made by piling GaN films upon a GaAs undersubstrate in vapor phase and eliminating the GaAs undersubstrate bends upward due to the inner stress owing to the misfit of lattice constants between GaN and GaAs.
    Type: Grant
    Filed: February 27, 2009
    Date of Patent: August 31, 2010
    Assignees: Sumitomo Electric Industries, Ltd., Sony Corporation
    Inventors: Masahiro Nakayama, Naoki Matsumoto, Koshi Tamamura, Masao Ikeda
  • Patent number: 7749325
    Abstract: A method of producing a separated GaN crystal body grown by vapor phase epitaxy on a substrate made of material different from GaN is provided. In this method, a nitride deposit is formed during the growth on a periphery of the substrate and GaN crystal body. The present method comprises the steps of: processing the periphery of the substrate to remove the nitride deposit; and, after the peripheral processing, separating the substrate from the GaN crystal body to make the substrate and the GaN crystal body independent of each other.
    Type: Grant
    Filed: January 22, 2007
    Date of Patent: July 6, 2010
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventor: Masahiro Nakayama