Abstract: A semiconductor integrated circuit device includes: a switching current observer for observing a switching current; a leakage current observer for observing a leakage current; a comparator which compares the switching current and the leakage current with each other; a threshold voltage controller for controlling a substrate bias voltage in order to make a ratio of the switching current and the leakage current constant; a delay observer for observing a delay amount; and a power supply voltage controller for controlling a power supply voltage in order to keep the delay amount in a predetermined range. In the semiconductor integrated circuit device, a process which enables the minimization of an operation power is carried out by controlling the threshold voltage to make the ratio of the switching current and the leakage current constant at a given clock frequency and controlling the power supply voltage to guarantee the operating speed.

Abstract: A precision alloy for die-casting contains aluminum, silicon and zinc, wherein on the basis of the overall mass, the content of aluminum is 40% by mass or more and 45% by mass or less, and the content of silicon is 2% by mass or more and 8% by mass or less. Also other solving means will be described.

Abstract: A semiconductor device comprising: a MIS type field effect transistor which comprises a semiconductor raised portion protruding from a substrate plane, a gate electrode extending over the semiconductor raised portion from the top onto the opposite side faces of the semiconductor raised portion, a gate insulation film existing between the gate electrode and the semiconductor raised portion, and source and drain regions provided in the semiconductor raised portion; an interlayer insulating film provided on a substrate including the transistor; and a buried conductor interconnect that is formed by filling in a trench formed in the interlayer insulating film with a conductor, wherein the buried conductor interconnect connects one of the source and drain regions of the semiconductor raised portion and another conductive portion below the interlayer insulating film.

Abstract: A dynamic semiconductor device is provided with a plurality of master step sections having hatch sections for temporarily storing input data and dynamic gate sections; a plurality of slave step sections, which are alternately connected with master step sections and provided with dynamic gate sections or with latch sections and dynamic gate sections; and a timing signal generating section for generating a signal for controlling operation of the master step sections and the slave step sections. The timing signal generating section supplies the latch sections with signals for storing data of the previous step before the data is erased.

Abstract: The present invention provides cyclic aminophenylalkanoic acid derivatives that act as agonists for human peroxisome proliferator-activated receptors (PPARs), in particular human PPAR? isoform, and are effective in the treatment of abnormal lipid metabolism, diabetes and other disorders. The present invention also provides addition salts of such cyclic aminophenylalkanoic acid derivatives and pharmaceutical compositions containing these compounds. Specifically, the present invention provides cyclic aminophenylalkanoic acid derivatives represented by the following general formula (1): , or pharmaceutically acceptable salts thereof.

Abstract: A level shifter in which short circuit current and the increase in delay are reduced when a first power source is controlled. In a level shifter for converting a signal level of a first logic circuit to which a first power source is supplied into a signal level of a second logic circuit to which a second power source is supplied, the circuit includes a switching circuit between a GND power source terminal of a level shift core circuit and a GND power source. The switching circuit is controlled by a third logic circuit which generates a control signal under control of the first power source, and a pull-up/pull-down circuit at an output of the level shift core circuit. The pull-up and/or pull-down circuit is controlled by the third logic circuit.

Abstract: There is provided a high-strength hot rolled steel sheet excellent in phosphatability, wherein a maximum depth (Ry) of pits and bumps, existing on a surface thereof, is not less than 10 ?m, and an average interval (Sm) of the pits and the bumps is not more than 30 ?m, meeting either a requirement for a load length ratio (tp40) of the pits and the bumps on the surface at not more than 20%, or a requirement for a difference between a load length ratio (tp60) and the load length ratio (tp40), at not less than 60%, or both thereof. The high-strength hot rolled steel sheet is capable of exhibiting stable and excellent phosphatability even if Mo highly effective for reinforcement in strength is added thereto in expectation of a higher strength.

Abstract: The invention provides a high strength cold rolled steel sheet having excellent chemical conversion treatment property stably even Mo is added aiming high strengthening. The surface property of the cold rolled steel sheet satisfies that the characteristic of 10 ?m or more of the maximum depth (Ry) of the unevenness and 30 ?m or less of the average spacing (Sm) of the unevenness, and that either one or more preferably both of, the characteristic of the load length ratio (tp40) of the unevenness of the surface is 20% or less, and the characteristic of the difference of the load length ratios (tp60) and (tp40) is 60% or more, is satisfied, and the crack of 3 ?m or less width and 5 ?m or more depth does not exist on the surface.

Abstract: A ? gate FinFET structure having reduced variations in off-current and parasitic capacitance and a method for production thereof are provided. The structure of an element is improved so that an off-current suppressing capability can be exhibited more strongly. A field effect transistor, wherein a first insulating film and a semiconductor region are provided so as to protrude upward with respect to the flat surface of a base, the field effect transistor has a gate electrode, a gate insulating film and a source/drain region, and a channel is formed at least on the side surface of the semiconductor region, wherein that the first insulating film is provided on an etch stopper layer composed of a material having an etching rate lower than at least the lowermost layer of the first insulating film for etching under a predetermined condition.

Abstract: A programmable semiconductor device of the invention includes: processing element unit executing a predetermined operation; input/output connection unit acting as a signal input part and/or a signal output part in processing element unit; interconnecting unit, comprised of a plurality of wires, connecting processing element unit via input/output connection unit; bidirectional repeater unit, arranged between the intersection points of interconnecting unit, performing disconnection, or driving interconnecting unit in the forward direction or in the reverse direction; and interconnection connecting unit, arranged at the intersection point, connecting interconnecting unit at the intersection point.

Abstract: A semiconductor device comprising a first semiconductor region and a second semiconductor region, (a) wherein a field effect transistor is comprised of the first semiconductor region comprising at least one semiconductor layer(s) protruding upward from a substrate, a gate electrode(s) formed via an insulating film such that the gate electrode(s) strides over the semiconductor layer(s) and source/drain regions provided in the semiconductor layer(s) on both sides of the gate electrode(s), whereby a channel region is formed in at least both sides of the semiconductor layer(s), (b) wherein the second semiconductor region comprises semiconductor layers protruding upward from the substrate and placed, at least opposing the first semiconductor region at both ends in the direction perpendicular to a channel current direction and the side surface of the semiconductor layers facing the first semiconductor region is parallel to the channel current direction.

Abstract: A level shifter in which short circuit current and the increase in delay are reduced when a first power source is controlled. In a level shifter for converting a signal level of a first logic circuit to which a first power source is supplied into a signal level of a second logic circuit to which a second power source is supplied, the circuit includes a switching circuit between a GND power source terminal of a level shift core circuit and a GND power source. The switching circuit is controlled by a third logic circuit which generates a control signal under control of the first power source, and a pull-up/pull-down circuit at an output of the level shift core circuit. The pull-up and/or pull-down circuit is controlled by the third logic circuit.

Abstract: A semiconductor integrated circuit device includes: a switching current observer for observing a switching current; a leakage current observer for observing a leakage current; a comparator which compares the switching current and the leakage current with each other; a threshold voltage controller for controlling a substrate bias voltage in order to make a ratio of the switching current and the leakage current constant; a delay observer for observing a delay amount; and a power supply voltage controller for controlling a power supply voltage in order to keep the delay amount in a predetermined range. In the semiconductor integrated circuit device, a process which enables the minimization of an operation power is carried out by controlling the threshold voltage to make the ratio of the switching current and the leakage current constant at a given clock frequency and controlling the power supply voltage to guarantee the operating speed.

Abstract: A semiconductor device having SRAM cell units each comprising a pair of a first driving transistor and a second driving transistor, a pair of a first load transistor and a second load transistor, and a pair of a first access transistor and a second access transistor, wherein each of the transistors comprises a semiconductor layer projecting upward from a substrate plane, a gate electrode extending on opposite sides of the semiconductor layer so as to stride over a top of the semiconductor layer, a gate insulating film interposed between the gate electrode and the semiconductor layer, and a pair of source/drain areas formed in the semiconductor layer; and the first and second driving transistors each have a channel width larger than that of at least either each of the load transistors or each of the access transistors.

Abstract: The present invention relates to a semiconductor device including a Fin type field effect transistor (FET) having a protrusive semiconductor layer protruding from a substrate plane, a gate electrode formed so as to straddle the protrusive semiconductor layer, a gate insulating film between the gate electrode and the protrusive semiconductor layer, and source and drain regions provided in the protrusive semiconductor layer, wherein the semiconductor device has on a semiconductor substrate an element forming region having a Fin type FET, a trench provided on the semiconductor substrate for separating the element forming region from another element forming region, and an element isolation insulating film in the trench; the element forming region has a shallow substrate flat surface formed by digging to a depth shallower than the bottom surface of the trench and deeper than the upper surface of the semiconductor substrate, a semiconductor raised portion protruding from the substrate flat surface and formed of a p

Abstract: A semiconductor device having SRAM cell units each comprising a pair of driving transistors, a pair of load transistors and a pair of access transistors, in which each of the transistors has a semiconductor layer projecting upward from a substrate plane, a gate electrode extending on opposite sides of the semiconductor layer so as to stride over a top of the semiconductor layer, a gate insulting film interposed between the gate electrode and the semiconductor layer, and a pair of source/drain areas formed in the semiconductor layer; a longitudinal direction of each semiconductor layer extends along a first direction; and between the adjacent SRAM cell units in the first direction, the semiconductor layer in one of the corresponding transistors is located on a center line of the semiconductor layer in the other transistor which center line extends along the first direction.

Abstract: Provided herein are aminoquinolones and pharmaceutically acceptable derivatives thereof. In certain embodiments, provided herein are compounds, compositions and methods for treating, preventing or ameliorating GSK-3 mediated diseases.

Abstract: A programmable semiconductor device of the invention includes: processing element unit executing a predetermined operation; input/output connection unit acting as a signal input part and/or a signal output part in processing element unit; interconnecting unit, comprised of a plurality of wires, connecting processing element unit via input/output connection unit; bidirectional repeater unit, arranged between the intersection points of interconnecting unit, performing disconnection, or driving interconnecting unit in the forward direction or in the reverse direction; and interconnection connecting unit, arranged at the intersection point, connecting interconnecting unit at the intersection point.

Abstract: The present invention relates to cyclic amino benzoic acid derivatives which are effective in therapy of lipid metabolism abnormality, diabetes and the like as a human peroxisome proliferators-activated receptor (PPAR) agonist, in particular, as an agonist against human PPAR? isoform, and addition salts thereof, and pharmaceutical compositions containing these compounds. A cyclic amino benzoic acid derivative represented by the general formula (1) [wherein a ring Ar represents an aryl group which may have substituent, or the like; Y represents a C1-C4 alkylene, C2-C4 alkenylene, C2-C4 alkynylene, or the like; Z represents an oxygen atom, sulfur atom or —(CH2)n— (n represents 0, 1 or 2); X represents a hydrogen atom, halogen atom, lower alkyl group which may be substituted with a halogen atom, or the like; R represents a hydrogen atom or lower alkyl group, and —COOR substitutes for an ortho position or metha position of binding position of ring W] or a pharmaceutically acceptable salt thereof.

Abstract: To provide a level shift circuit in which the margin of level shift operation is prevented from deteriorating when the potential difference between a first power supply and a second power supply is large. A level shift circuit for changing the signal level in a first logic circuit fed from a first power supply to the signal level in a second logic circuit fed from a second power supply, comprises: a pull-up and/or pull-down circuit fed from the second power supply for pulling up and/or pulling down the output of a level shift core circuit; and a control circuit fed from the second power supply, which receives level shift input signals and level shift output signals for controlling the pull-up and/or pull-down circuit.

Abstract: A photopolymerizable composition comprising an addition polymerizable compound, an N-aryl-.alpha.-amino acid and a photosensitizer capable of absorbing a light having a wavelength of 300 nm or more such as thioxanthones, isoalloxazines, coumarines, and the like is excellent in sensitivity to irradiated light and is suitable for preparing relief images, photoresists, etc.