Patents by Inventor Masahiro Ogata

Masahiro Ogata has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5289428
    Abstract: A multiport memory is provided which permits both random access and serial access. In order to reduce parasitic capacitance and improve operating speed, the serial input/output lines are each divided into two parts at their middle points. Sense amplifiers for the serial input/output lines are provided at upper and lower ends of the serial access memory elements to respectively amplify signals from the divided lines. Additional features are provided for improving both the serial and random operation. For example, during the serial read mode, the column selector for random access is simultaneously operated, and read data passing through the random access column selector is used as head data for the serial output operation to be delivered through the serial output circuit. Also, a serial selector can be controlled by a select signal formed by a Gray Code counter to improve operating speed.
    Type: Grant
    Filed: November 6, 1992
    Date of Patent: February 22, 1994
    Assignee: Hitachi Ltd., and Hitachi VLSI Engineering Corp.
    Inventors: Katsuyuki Sato, Miki Matsumoto, Sadayuki Ohkuma, Masahiro Ogata, Masahiro Yoshida
  • Patent number: 5161120
    Abstract: A data output buffer is provided in connection with a semiconductor memory, such as a pseudostatic RAM, which is capable of high speed operation with respect to memory data readout. The buffer includes a latch circuit comprising a pair of NAND gate circuits having input and output terminals connected in cross connection, a pair of precharge MOSFETs provided respectively between the noninverted and inverted input terminals of the latch circuit, a pair of CMOS NAND gates which transfer the inverted signal of the latch circuit according to an inverted timing signal and a pair of series-connected MOSFETs effecting a pull-up/pull-down arrangement which receives the inverted signal of the output signal of the NAND gates.
    Type: Grant
    Filed: March 20, 1990
    Date of Patent: November 3, 1992
    Assignees: Hitachi, Ltd., Hitachi VLSI Engineering Corp.
    Inventors: Takeshi Kajimoto, Yutaka Shimbo, Katsuyuki Sato, Masahiro Ogata, Kanehide Kenmizaki, Shouji Kubono, Nobuo Kato, Kiichi Manita, Michitaro Kanamitsu
  • Patent number: 5115413
    Abstract: A multiport memory is provided which permits both random access and serial access. In order to reduce parasitic capacitance and improve operating speed, the serial input/output lines are each divided into two parts at their middle points. Sense amplifiers for the serial input/output lines are provided at upper and lower ends of the serial access memory elements to respectively amplify signals from the divided lines. Additional features are provided for improving both the serial and random operation. For example, during the serial read mode, the column selector for random access is simultaneously operated, and read data passing through the random access column selector is used as head data for the serial output operation to be delivered through the serial output circuit. Also, a serial selector can be controlled by a select signal formed by a Gray Code counter to improve operating speed.
    Type: Grant
    Filed: March 20, 1990
    Date of Patent: May 19, 1992
    Assignees: Hitachi, Ltd., Hitachi VLSI Engineering Corporation
    Inventors: Katsuyuki Sato, Miki Matsumoto, Sadayuki Ohkuma, Masahiro Ogata, Masahiro Yoshida
  • Patent number: 5083911
    Abstract: A pressure slip casing apparatus for producing a sanitary ware such as a toilet bowl, comprises lifting hydraulic cylinder means secured to said top member of a stationary frame; a pair of suspending devices supported by a base plate attached to said lifting hydraulic cylinder means; an interlocking mechanism for operatively connecting said suspending devices to each other; and a hydraulic cylinder device for moving a suspending devices towards and away from each other through the action of said interlocking mechanism. A mold part and a core mold part are attached to said base of said stationary frame and to the lower surface of said base plate, respectively.
    Type: Grant
    Filed: August 1, 1990
    Date of Patent: January 28, 1992
    Assignee: Toto Ltd.
    Inventors: Masanobu Hisaeda, Satoru Saitou, Masahiro Ogata
  • Patent number: 4948087
    Abstract: An apparatus for pressure molding ceramic articles includes at least one split mold including a core mold and an outer mold which are joined together for defining a pressure mold cavity therebetween. At least the bottom surface of the pressure mold cavity is inclined longitudinally and laterally, while the split mold per se is not inclined and the slip supply passage for supplying the slip into the pressure mold cavity communicates with the lowermost end of the pressure mold cavity. Due to the above construction, it is no longer necessary to incline the entirety of the split molds so that the frame structure of the apparatus can be vertically constructed on a horizontal floor which permits easy construction installation and adjustment and maintenance of the apparatus. Furthermore, since the bottom surface of the pressure mold cavity is inclined longitudinally and laterally, the surplus slip is discharged completely and smoothly, and does not remain in the pressure mold cavity.
    Type: Grant
    Filed: February 21, 1989
    Date of Patent: August 14, 1990
    Assignee: Toto Ltd.
    Inventors: Masanobu Hisaeda, Satoru Saitou, Masahiro Ogata
  • Patent number: 4912674
    Abstract: A mask-programmed ROM includes depletion type load MOSFETs provided between data lines in a memory array and a power supply voltage, the MOSFETs having a ground potential of the circuit applied to their gates. Reading of data is carried out by an amplifying MOSFET which supplies a current to a selected data line through a depletion type MOSFET which is supplied at its gate with the circuit ground potential. Thus, bias voltages which are respectively applied to the data lines and a sense amplifier which receives a signal read out from a selected data line are made equal to each other, thereby achieving a high-speed read operation.
    Type: Grant
    Filed: February 14, 1989
    Date of Patent: March 27, 1990
    Assignees: Hitachi, Ltd., Hitachi VLSI Engineering Corp.
    Inventors: Youichi Matsumoto, Ryuuji Shibata, Isamu Kobayashi, Satoshi Meguro, Kouichi Nagasawa, Hideo Meguro, Hisahiro Moriuchi, Masahiro Ogata, Kikuo Sakai, Toshifumi Takeda
  • Patent number: 4839860
    Abstract: A semiconductor memory includes a dummy cell for forming a reference potential, a read-only memory cell, and a differential amplifier circuit which receives the reference potential formed by the dummy cell and a signal read out from the memory cell. The differential amplifier circuit is dynamically operated so that the semiconductor memory is made smaller in power consumption and size than conventional units. Moreover, in order to reduce the power consumption, the memory cell is brought into the nonselection state when a predetermined time has passed after being selected. In addition, the semiconductor memory is provided with a compensating circuit in order to make the value of the capacitance connected to a word line for transmitting a selecting signal to the memory cell and the value of the capacitance connected to a dummy word line for transmitting a selecting signal to the dummy cell substantially equal to each other.
    Type: Grant
    Filed: January 17, 1986
    Date of Patent: June 13, 1989
    Assignees: Hitachi, Ltd., Hitachi Microcomputer Engineering Ltd.
    Inventors: Takashi Shinoda, Kikuo Sakai, Masahiro Ogata, Hiroshi Kawamoto, Yoshiaki Onishi, deceased, by Junko Onishi, administratrix
  • Patent number: 4805143
    Abstract: A mask-programmed ROM includes depletion type load MOSFETs provided between data lines in a memory array and a power supply voltage, the MOSFETs having a ground potential of the circuit applied to their gates. Reading of data is carried out by an amplifying MOSFET which supplies a current to a selected data line through a depletion type MOSFET which is supplied at its gate with the circuit ground potential. Thus, bias voltages which are respectively applied to the data lines and a sense amplifier which receives a signal read out from a selected data line are made equal to each other, thereby achieving a high-speed read operation.
    Type: Grant
    Filed: January 12, 1987
    Date of Patent: February 14, 1989
    Assignees: Hitachi Ltd., Hitachi VLSI Engineering Corp.
    Inventors: Youichi Matsumoto, Ryuuji Shibata, Isamu Kobayashi, Satoshi Meguro, Kouichi Nagasawa, Hideo Meguro, Hisahiro Moriuchi, Masahiro Ogata, Kikuo Sakai, Toshifumi Takeda
  • Patent number: 4604749
    Abstract: YA semiconductor memory is provided with memory cells for storing a plurality of sets of data, each of the sets having check bits. A selecting circuit selects some of the memory cells to form a set in response to a first address signal. The circuit includes an error correcting code circuit, a tristate circuit and a control circuit which forms a control signal to control the tristate circuit. Output terminals of the tristate circuit are coupled with external output terminals of the semiconductor memory. Also, the tristate circuit is controlled by the control signal to bring the external circuit terminals into high impedance at least during the time when the error correcting code circuit is delivering indefinite data.
    Type: Grant
    Filed: June 9, 1983
    Date of Patent: August 5, 1986
    Assignees: Hitachi, Ltd., Hitachi Microcomputer Engineering Ltd.
    Inventors: Takashi Shinoda, Kikuo Sakai, Masahiro Ogata, Hiroshi Kawamoto, Yoshiaki Onishi, deceased, Junko Onishi, administratrix
  • Patent number: 4437135
    Abstract: In the past, it has been a problem in integrated circuits using MOSFETs that the gate insulating film of a transmission gate MOSFET is broken down when an abnormally high voltage such as is caused by frictional static electricity is applied to its drain region. This breakdown of the gate insulating film cannot be prevented merely by limiting the voltage level applied to the drain region to a level below the breakdown withstand voltage of the gate insulating film. The reason for this is that even with such voltage limiting, the breakdown of the gate insulating film can still occur when local heating is generated by a relatively large breakdown current flowing through the drain junction. To prevent such a breakdown of the gate insulating film, therefore, a resistance element for limiting the breakdown current is connected in series with the drain region of the transmission gate MOSFET.
    Type: Grant
    Filed: November 6, 1981
    Date of Patent: March 13, 1984
    Assignees: Hitachi, Ltd., Hitachi Microcomputer Engineering, Ltd.
    Inventors: Masahiro Ogata, Osamu Sakai
  • Patent number: D313782
    Type: Grant
    Filed: June 28, 1988
    Date of Patent: January 15, 1991
    Assignee: The Yokohama Rubber Co., Ltd.
    Inventors: Hirohisa Hazama, Masahiro Ogata, Izumi Kuramochi