Patents by Inventor Masahiro Okamoto
Masahiro Okamoto has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11962972Abstract: To enhance a sound image localization effect and to ensure a good viewing state in which an image or video and audio have a sense of unity. Provided is a display in which an image is displayed in a display surface, a rear cover disposed on a rear side of the display, a first speaker disposed between the display and the rear cover, and a second speaker disposed between the display and the rear cover and positioned higher than the first speaker. The second speaker outputs audio according to operation of a piezoelectric element, and has a higher audio output band than the first speaker. This enables a user to feel as if the audio is being output from the display being viewed, which enhances the sound image localization effect and ensures a good viewing state in which an image or video and audio have a sense of unity.Type: GrantFiled: November 21, 2019Date of Patent: April 16, 2024Assignee: SONY GROUP CORPORATIONInventors: Masahiro Takahashi, Tatsuya Sakata, Tetsuya Shiroishi, Shigemi Oguchi, Kazumasa Okamoto, Ryosuke Nakajima
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Publication number: 20240090140Abstract: A component-incorporated substrate of multi-layer structure includes: a first printed wiring base having an opening; a second printed wiring base in a first side of the first printed wiring base; a third printed wiring base in a second side of the first printed wiring base; an electronic component housed in the opening of the first printed wiring base; a via penetrating one or more of the first printed wiring base, the second printed wiring base and the third printed wiring base; and an adhesive layer that fills a gap between the electronic component and the opening, a gap between the first printed wiring base and the second printed wiring base, and a gap between the first printed wiring base and the third printed wiring base.Type: ApplicationFiled: November 22, 2023Publication date: March 14, 2024Applicant: FUJIKURA LTD.Inventor: Masahiro Okamoto
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Patent number: 11871524Abstract: A component-incorporated substrate of multi-layer structure includes: a plurality of printed wiring base members that are batch-laminated via an adhesive layer, with the plurality of printed wiring base members including a resin base member that includes a wiring pattern on at least one surface thereof and a via connected to the wiring pattern; an opening disposed in at least one printed wiring base member that is sandwiched on both sides by other printed wiring base members of the plurality of printed wiring base members; and an electronic component disposed in the opening. At least part of the wiring pattern of the printed wiring base member where the opening is formed is disposed in a frame shape surrounding the opening, in a periphery of the opening.Type: GrantFiled: August 21, 2017Date of Patent: January 9, 2024Assignee: Fujikura Ltd.Inventor: Masahiro Okamoto
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Publication number: 20210204414Abstract: A component-incorporated substrate of multi-layer structure includes: a plurality of printed wiring base members that are batch-laminated via an adhesive layer, with the plurality of printed wiring base members including a resin base member that includes a wiring pattern on at least one surface thereof and a via connected to the wiring pattern; an opening disposed in at least one printed wiring base member that is sandwiched on both sides by other printed wiring base members of the plurality of printed wiring base members; and an electronic component disposed in the opening. At least part of the wiring pattern of the printed wiring base member where the opening is formed is disposed in a frame shape surrounding the opening, in a periphery of the opening.Type: ApplicationFiled: August 21, 2017Publication date: July 1, 2021Applicant: FUJIKURA LTD.Inventor: Masahiro Okamoto
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Publication number: 20190388993Abstract: A hybrid welding apparatus selectively switches between MAG welding and TIG welding. The apparatus includes a control device (1), which includes a welding output unit (10) for outputting a welding voltage and a welding current. When MAG welding is selected, the positive terminal of the welding output unit (10) is connected to a MAG welding torch (2), and the negative terminal is connected to a welding base material (4). Meanwhile, when TIG welding is selected, the positive terminal of the welding output unit (10) is connected to the welding base material, and the negative terminal is connected to a TIG welding torch (3).Type: ApplicationFiled: September 5, 2019Publication date: December 26, 2019Inventors: HARUKI TANAKA, KAZUO KITA, MASAHIRO OKAMOTO, KUNITOSHI MORITA
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Patent number: 10383231Abstract: Provided is a component-embedded board which includes: a first board including a first insulation layer, a first conductive layer formed on a second face of the first insulation layer, and an interlayer conductive portion penetrating the first insulation layer to be connected to the first conductive layer and protruding from a first face of the first insulation layer; an electric component connected to the interlayer conductive portion; and a second board including a second insulation layer having an opening portion incorporating the electric component, and a second conductive layer formed on at least either one of a first face and a second face of the second insulation layer. The second conductive layer includes a frame portion. The opening portion is formed so as to penetrate the second insulation layer in a thickness direction thereof over the entirety of the inner region of the frame portion.Type: GrantFiled: February 8, 2013Date of Patent: August 13, 2019Assignee: FUJIKURA LTD.Inventors: Yoshinori Sano, Masahiro Okamoto
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Patent number: 9699921Abstract: A multi-layer wiring board that has stacked therein a first printed wiring bases on at least one surface of which a wiring pattern is formed and in which a conductive paste via is formed, that includes an electronic component terminal and a board terminal whose terminal pitch differs from that of the electronic component terminal, and that has an electronic component installed thereon via the electronic component terminal, wherein a second wiring base whose wiring pitch is smaller than that of the first wiring base is built in to a lower portion of an installing portion of the electronic component via the first wiring base, and the second wiring base is connected to the electronic component terminal via the conductive paste via of the first wiring base, has formed on both surfaces thereof a pattern that enlarges the terminal pitch from the electronic component terminal to the board terminal, and includes a via that connects the pattern of the both surfaces.Type: GrantFiled: August 1, 2014Date of Patent: July 4, 2017Assignee: FUJIKURA LTD.Inventor: Masahiro Okamoto
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Patent number: 9591767Abstract: A component built-in board comprises stacked therein a plurality of printed wiring bases having a wiring pattern and a via formed on/in a resin base thereof, and comprises an electronic component built in thereto, wherein at least a portion of the plurality of printed wiring bases include a thermal wiring in the wiring pattern and include a thermal via in the via, at least one of the plurality of printed wiring bases has formed therein an opening where the electronic component is built, and has formed therein a heat-conducting layer and closely attached to a surface on an opposite side to an electrode formation surface of the electronic component built in to the opening, and the electronic component is fixed in the opening by an adhesive layer stacked on the heat-conducting layer, via a hole formed in a region facing onto the opening of the heat-conducting layer.Type: GrantFiled: May 29, 2014Date of Patent: March 7, 2017Assignee: FUJIKURA LTD.Inventors: Kazuhisa Itoi, Masahiro Okamoto
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Patent number: 9282628Abstract: A component built-in board, wherein at least two layers of a plurality of printed wiring bases are disposed on a rear surface side of an electronic component; the at least two layers of the printed wiring bases include a heat radiation-dedicated wiring pattern that is disposed above the rear surface of the electronic component; the heat radiation-dedicated wiring pattern is formed such that a heat radiation-dedicated wiring line and a signal-dedicated wiring line are continuous; a via includes a plurality of heat radiation-dedicated vias which connects the rear surface of the electronic component and the heat radiation-dedicated wiring pattern; and the heat radiation-dedicated wiring pattern is continuous from a place where connected to the heat radiation-dedicated via to be connected also to another via disposed at an outer peripheral side of the electronic component.Type: GrantFiled: January 17, 2014Date of Patent: March 8, 2016Assignee: FUJIKURA LTD.Inventor: Masahiro Okamoto
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Publication number: 20160037630Abstract: A multi-layer wiring board that has stacked therein a first printed wiring bases on at least one surface of which a wiring pattern is formed and in which a conductive paste via is formed, that includes an electronic component terminal and a board terminal whose terminal pitch differs from that of the electronic component terminal, and that has an electronic component installed thereon via the electronic component terminal, wherein a second wiring base whose wiring pitch is smaller than that of the first wiring base is built in to a lower portion of an installing portion of the electronic component via the first wiring base, and the second wiring base is connected to the electronic component terminal via the conductive paste via of the first wiring base, has formed on both surfaces thereof a pattern that enlarges the terminal pitch from the electronic component terminal to the board terminal, and includes a via that connects the pattern of the both surfaces.Type: ApplicationFiled: August 1, 2014Publication date: February 4, 2016Applicant: FUJIKURA LTD.Inventor: Masahiro Okamoto
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Publication number: 20150359103Abstract: Provided is a component-embedded board which includes: a first board including a first insulation layer, a first conductive layer formed on a second face of the first insulation layer, and an interlayer conductive portion penetrating the first insulation layer to be connected to the first conductive layer and protruding from a first face of the first insulation layer; an electric component connected to the interlayer conductive portion; and a second board including a second insulation layer having an opening portion incorporating the electric component, and a second conductive layer formed on at least either one of a first face and a second face of the second insulation layer. The second conductive layer includes a frame portion. The opening portion is formed so as to penetrate the second insulation layer in a thickness direction thereof over the entirety of the inner region of the frame portion.Type: ApplicationFiled: February 8, 2013Publication date: December 10, 2015Applicant: FUJIKURA LTD.Inventors: Yoshinori SANO, Masahiro OKAMOTO
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Patent number: 8941016Abstract: A laminated wiring board, includes: a first substrate in which a conductor circuit is formed on one surface of an insulating layer and an adhesive layer is formed on an other surface of the insulating layer, and conductors are formed in via holes that pass through the insulating layer and the adhesive layer so that the conductor circuit is partially exposed therefrom; an electronic component electrically connected to the conductor circuit by allowing electrodes of the electronic component to be connected to the conductors; an embedding member arranged around the electronic components so that the electronic component is embedded therein; and a second substrate having an adhesive layer laminated to face the adhesive layer of the first substrate and sandwich the electronic component and the embedding member, wherein each of the electrodes of the electronic component is continuous with the conductor circuit through two or more of the conductors.Type: GrantFiled: January 4, 2013Date of Patent: January 27, 2015Assignee: Fujikura Ltd.Inventor: Masahiro Okamoto
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Publication number: 20140268574Abstract: A component built-in board comprises stacked therein a plurality of printed wiring bases having a wiring pattern and a via formed on/in a resin base thereof, and comprises an electronic component built in thereto, wherein at least a portion of the plurality of printed wiring bases include a thermal wiring in the wiring pattern and include a thermal via in the via, at least one of the plurality of printed wiring bases has formed therein an opening where the electronic component is built, and has formed therein a heat-conducting layer and closely attached to a surface on an opposite side to an electrode formation surface of the electronic component built in to the opening, and the electronic component is fixed in the opening by an adhesive layer stacked on the heat-conducting layer, via a hole formed in a region facing onto the opening of the heat-conducting layer.Type: ApplicationFiled: May 29, 2014Publication date: September 18, 2014Applicant: FUJIKURA LTD.Inventors: Kazuhisa Itoi, Masahiro Okamoto
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Publication number: 20140202741Abstract: A component built-in board, wherein at least two layers of a plurality of printed wiring bases are disposed on a rear surface side of an electronic component; the at least two layers of the printed wiring bases include a heat radiation-dedicated wiring pattern that is disposed above the rear surface of the electronic component; the heat radiation-dedicated wiring pattern is formed such that a heat radiation-dedicated wiring line and a signal-dedicated wiring line are continuous; a via includes a plurality of heat radiation-dedicated vias which connects the rear surface of the electronic component and the heat radiation-dedicated wiring pattern; and the heat radiation-dedicated wiring pattern is continuous from a place where connected to the heat radiation-dedicated via to be connected also to another via disposed at an outer peripheral side of the electronic component.Type: ApplicationFiled: January 17, 2014Publication date: July 24, 2014Applicant: FUJIKURA LTD.Inventor: Masahiro Okamoto
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Patent number: 8726495Abstract: A base material (20) is arranged on top of at least one first internal layer base material (10), and a second internal base material (30) is arranged underneath the base material (10). And thereafter a surface layer circuitry conductive foil (40) is arranged underneath the base material (30), and subsequently these materials are colaminated for forming a colaminated body (80). While this colaminating operation, conductive portions being formed in the base materials 10, 30 are aligned to electrically connect one another for forming an internal circuitry. And thereafter, an interlayer conductive portion (51) being electrically connected to the internal circuitry is formed, and a minute circuitry is formed on the top of the base material (20) and the conductive foil (40) accordingly.Type: GrantFiled: June 16, 2008Date of Patent: May 20, 2014Assignee: Fujikura Ltd.Inventors: Osamu Nakao, Reiji Higuchi, Syouji Ito, Masahiro Okamoto
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Patent number: 8449496Abstract: The present invention is a peritoneal function testing method characterized by using a ratio MTACun/MTACc calculated using MTACun and MTACc as an index for a peritoneal function test, where MTACun is an overall mass transfer-area coefficient for urea nitrogen and MTACc is an overall mass transfer-area coefficient for creatinine. The use of MTACun/c of the present invention in this way enables examination of the future peritoneal function of a patient (a mechanism of deterioration in peritoneal function). To be specific, MTACun and MTACc can be obtained by computing Pyle-Popovich model. In addition, the peritoneal function testing method may further calculate a permeability coefficient for cell pores (LPSC) and an overall permeability coefficient (LPS) from Three-Pore Theory model while obtaining a ratio LPSC/LPS calculated using the LPSC and the LPS, and may use the LPSC/LPS ratio and the MTACun/MTACc ratio as indexes for the peritoneal function test.Type: GrantFiled: May 21, 2009Date of Patent: May 28, 2013Assignee: JMS Co., Ltd.Inventors: Hiroyuki Hamada, Masahiro Okamoto
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Patent number: 8444593Abstract: A peritoneal function testing method uses a ratio of MTACun/MTACc, calculated using MTACun and MTACc, as an index for a peritoneal function test, wherein MTACun is an overall mass transfer-area coefficient for urea nitrogen and MTACun is an overall mass transfer-area coefficient for creatinine. The use of MTACun/MTACc enables examination of the future peritoneal function of a patient (a mechanism of deterioration in peritoneal function). To be specific, MTACun and MTACc can be obtained by computing a Pyle-Popovich model. In addition, the peritoneal function testing method further calculates a permeability coefficient for cell pores (LpSC) and an overall permeability coefficient (LPS) from a Three-Pore Theory model while obtaining a ratio of LPSC/LPS calculated using the LPSC and the LPS. The LPSC/LPS ratio and the MTACun/MTACc ratio can be used as indexes for the peritoneal function test.Type: GrantFiled: May 10, 2011Date of Patent: May 21, 2013Assignee: JMS Co., Ltd.Inventors: Hiroyuki Hamada, Masahiro Okamoto
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Patent number: 8303532Abstract: A peritoneal function testing apparatus tests the peritoneal function of a dialysis patient easily and with high accuracy. Standards of four kinetic parameters (CCr, Kt/V, MTACu, and MTACc) available in a definite dialysis guideline are computed in accordance with a relational expression, and a curve showing the relation between MTACu/c and the drained fluid volume is indicated in a graph together with the PET data of the patient which has been prepared separately. Thus, the peritoneal function can be evaluated based on the relative position of the patient's data and the curve showing the standard values in the graph.Type: GrantFiled: August 22, 2006Date of Patent: November 6, 2012Assignee: JMS Co., Ltd.Inventors: Hiroyuki Hamada, Masahiro Okamoto, Shinji Namoto, Tomokazu Karino
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Patent number: 8123715Abstract: The present invention is a peritoneal dialysis and hemodialysis hybrid-remedy planning method using an index that is shared by both peritoneal dialysis and hemodialysis and indicates an effect of dialysis. To be specific, the index is M/C(0)/VB, which is obtained by dividing a ratio M/C(0)—where M is a removal amount of a solute for a fixed time period, and C(0) is a concentration of the solute in blood before the dialysis—by a patient's body fluid volume, VB. The present invention is capable of representing the dialysis effect of PD and HD as an integrated sum, and achieving concise and explicit PD and HD hybrid-remedy planning.Type: GrantFiled: May 14, 2004Date of Patent: February 28, 2012Assignee: JMS Co., Ltd.Inventors: Hiroyuki Hamada, Masahiro Okamoto
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Patent number: 8088094Abstract: The present invention is a peritoneal dialysis and hemodialysis hybrid-remedy planning method using an index that is shared by both peritoneal dialysis and hemodialysis and indicates an effect of dialysis. To be specific, the index is M/C(0)/VB, which is obtained by dividing a ratio M/C(0)—where M is a removal amount of a solute for a fixed time period, and C(0) is a concentration of the solute in blood before the dialysis—by a patient's body fluid volume, VB. The present invention is capable of representing the dialysis effect of PD and HD as an integrated sum, achieving concise and explicit PD and HD hybrid-remedy planning.Type: GrantFiled: September 30, 2009Date of Patent: January 3, 2012Assignee: JMS Co., Ltd.Inventors: Hiroyuki Hamada, Masahiro Okamoto