Abstract: Provided is a shopping cart capable of simplifying equipment of a storage area of the shopping cart. A shopping cart allowed to be nested in a front-rear direction, including: a cart body; a battery configured to supply power to an electronic device attached to the cart body and displayed commodity information read by a reading device; a power receiving portion provided on a front side of the cart body and configured to be electrically connectable to an external power supply; and a power transmitting portion provided on a rear surface side of the power receiving portion and configured to supply power to a power receiving portion of another shopping cart nested in the shopping cart. Each of the power receiving portion and the power transmitting portion is provided with a magnet configured for holding a relative position.

Abstract: A method evaluates an edge shape of a silicon wafer, in which as shape parameters in a wafer cross section, when defining a radial direction reference L1, a radial direction reference L2, an intersection point P1, a height reference plane L3, h1 [?m], h2 [?m], a point Px3, a straight line Lx, an angle ?x, a point Px0, ? [?m], a point Px1, and a radius Rx [?m], the edge shape of the silicon wafer is measured, values of the shape parameters h1, h2, and ? are set, the shape parameters Rx and ?x are calculated in accordance with the definition based on measurement data of the edge shape, and the edge shape of the silicon wafer is determined from the calculated Rx and ?x to be evaluated. Consequently, a method evaluates an edge shape of a silicon wafer capable of preventing an occurrence of trouble.

Abstract: A method evaluates an edge shape of a silicon wafer, in which as shape parameters in a wafer cross section, when defining a radial direction reference L1, a radial direction reference L2, an intersection point P1, a height reference plane L3, h1 [?m], h2 [?m], a point Px3, a straight line Lx, an angle ?x, a point Px0, ? [?m], a point Px1, and a radius Rx [?m], the edge shape of the silicon wafer is measured, values of the shape parameters h1, h2, and ? are set, the shape parameters Rx and ?x are calculated in accordance with the definition based on measurement data of the edge shape, and the edge shape of the silicon wafer is determined from the calculated Rx and ?x to be evaluated. Consequently, a method evaluates an edge shape of a silicon wafer capable of preventing an occurrence of trouble.

Abstract: A silicon epitaxial wafer including: a second intermediate epitaxial layer on a silicon substrate produced by being cut from a silicon single crystal ingot grown by the CZ method so as to have a carbon concentration ranging from 3×1016 to 2×1017 atoms/cm3, a first intermediate epitaxial layer doped with a dopant, and an epitaxial layer of a device forming region stacked on the first intermediate epitaxial layer, and to a method of producing this wafer. Also providing an industrially excellent silicon epitaxial wafer that is produced with a silicon substrate doped with carbon and used as a semiconductor device substrate such as a memory, a logic, or a solid-state image sensor, and a method of producing this silicon epitaxial wafer.

Abstract: A method of producing a phosphorus-doped silicon single crystal, including pulling the phosphorus-doped silicon single crystal from a silicon melt doped with phosphorus by Magnetic field applied Czochralski (MCZ) method, wherein the phosphorus is doped such that a phosphorus concentration of the phosphorus-doped silicon single crystal is 2×1016 atoms/cm3 or more, and a horizontal magnetic field is applied to the silicon melt with a central magnetic field strength of 2,000 gauss or more such that the phosphorus-doped silicon single crystal to be produced has an oxygen concentration of 1.6×1018 atoms/cm3 (ASTM'79) or more. A method of producing a silicon single crystal that is heavily doped with phosphorus and has an oxygen concentration of 1.6×1018 atoms/cm3 (ASTM'79) or more.

Abstract: A method for heat-treating a silicon single crystal wafer by an RTA treatment, including: putting a silicon single crystal wafer having an Nv region for the entire plane of the silicon single crystal wafer or an Nv region containing an OSF region for the silicon single crystal wafer entire plane into an RTA furnace, performing pre-heating at temperature lower than temperature at which silicon reacts with NH3 while supplying gas that contains NH3 into the RTA furnace, subsequently stopping the supply of the gas containing NH3 and starting supply of Ar gas to start an RTA treatment under Ar gas atmosphere in which the NH3 gas remains. This provide a method for heat-treating a silicon single crystal wafer that give gettering capability without degrading TDDB properties even to a silicon single crystal wafer in which the entire plane is an Nv region or an Nv region containing an OSF region.

Abstract: A method for manufacturing an epitaxial wafer for manufacture of an image pickup device, wherein, before the growth of the epitaxial layer, a thickness X of a region where oxygen concentration in the epitaxial layer becomes 4×1017 atoms/cm3 or more after the manufacture of the image pickup device is calculated and, in the growth of the epitaxial layer, the epitaxial layer is grown with a thickness such that a thickness of a region where the oxygen concentration in the epitaxial layer is less than 4×1017 atoms/cm3 after the manufacture of the image pickup device is 6 ?m or more in addition to the thickness X. As a result, it is possible to provide the epitaxial wafer in which an adverse effect of an impurity such as oxygen in the silicon wafer is not exerted on an image pickup device forming portion of the epitaxial layer and a manufacturing method thereof.

Abstract: A silicon epitaxial wafer including: a second intermediate epitaxial layer on a silicon substrate produced by being cut from a silicon single crystal ingot grown by the CZ method so as to have a carbon concentration ranging from 3×1016 to 2×1017 atoms/cm3, a first intermediate epitaxial layer doped with a dopant, and an epitaxial layer of a device forming region stacked on the first intermediate epitaxial layer, and to a method of producing this wafer. Also providing an industrially excellent silicon epitaxial wafer that is produced with a silicon substrate doped with carbon and used as a semiconductor device substrate such as a memory, a logic, or a solid-state image sensor, and a method of producing this silicon epitaxial wafer.

Abstract: A method of producing a phosphorus-doped silicon single crystal, including pulling the phosphorus-doped silicon single crystal from a silicon melt doped with phosphorus by Magnetic field applied Czochralski (MCZ) method, wherein the phosphorus is doped such that a phosphorus concentration of the phosphorus-doped silicon single crystal is 2×1016 atoms/cm3 or more, and a horizontal magnetic field is applied to the silicon melt with a central magnetic field strength of 2,000 gauss or more such that the phosphorus-doped silicon single crystal to be produced has an oxygen concentration of 1.6×1018 atoms/cm3 (ASTM'79) or more. A method of producing a silicon single crystal that is heavily doped with phosphorus and has an oxygen concentration of 1.6×1018 atoms/cm3 (ASTM'79) or more.

Abstract: A method for manufacturing an epitaxial wafer for manufacture of an image pickup device, wherein, before the growth of the epitaxial layer, a thickness X of a region where oxygen concentration in the epitaxial layer becomes 4×1017 atoms/cm3 or more after the manufacture of the image pickup device is calculated and, in the growth of the epitaxial layer, the epitaxial layer is grown with a thickness such that a thickness of a region where the oxygen concentration in the epitaxial layer is less than 4×1017 atoms/cm3 after the manufacture of the image pickup device is 6 ?m or more in addition to the thickness X. As a result, it is possible to provide the epitaxial wafer in which an adverse effect of an impurity such as oxygen in the silicon wafer is not exerted on an image pickup device forming portion of the epitaxial layer and a manufacturing method thereof.

Abstract: A method of manufacturing a single crystal based on a Czochralski method of applying a horizontal magnetic field, wherein the single crystal is pulled in such a manner that a radial magnetic field intensity gradient ?Br/?Rc in a direction connecting central points of magnetic field generation coils exceeds 5.5 (Gauss/mm) and becomes 10 (Gauss/mm) or below where an origin O is a central part of the single crystal on a solid-liquid interface, ?Br (Gauss) is a variation in a magnetic field intensity from the origin O to a crucible inner wall on a surface of a melt, and ?Rc (mm) is a radial distance from the origin O to the crucible inner wall on the surface of the melt.

Abstract: The present invention is a quartz glass crucible 5 for pulling a silicon single crystal, comprising at least an outer layer portion 23 being a translucent glass layer containing multiple bubbles in it and an inner layer portion 24 being a transparent quartz glass layer having no bubbles and a smooth surface, formed on the inner surface of the outer layer portion 23, wherein the outer layer portion 23 contains bubbles of 0.1 to 0.3 mm in diameter at the density of 1.5 to 5.0×104 bubbles/cm3. Thus, there are provided a quartz glass crucible for pulling a silicon single crystal, the quartz glass crucible being increased in mechanical strength, making it possible to suppress deformation of a quartz glass crucible for pulling a silicon single crystal during a single crystal pulling process, thereby prevent degradation in yield rate due to dislocation in a single crystal and make the manufacture of a silicon single crystal highly efficient and a method of manufacturing the same quartz glass crucible.

Abstract: This invention provides a process for producing a single crystal by a Chokralsky method in which a horizontal magnetic field is applied, characterized in that a single crystal is pulled up so that the radial magnetic field strength gradient ?Br/?Rc in such a direction that centers of magnetic field generation coils (25) are connected, is more than 5.5 (gauss/mm) and not more than 10 (gauss/mm) wherein ?Br represents the amount of a variation in magnetic field strength from an original point (O) as the center part on a solid-liquid interface of a single crystal (12) to the inner wall (A) of a crucible on the surface of a melt, gauss; and ?Rc represents a radial distance from the original point (O) to the inner wall (A) of the crucible on the surface of the melt, mm.

Abstract: The present invention is an SOI wafer in which at least a silicon active layer is formed over a support substrate via an insulator film or on a support substrate directly, wherein, at least, the silicon active layer consists of a P(phosphorus)-doped silicon single crystal grown by Czochralski method, which is occupied by N region and/or defect-free I region, and contains Al (aluminum) with concentration of 2×1012 atoms/cc or more. There can be provided with ease and at low cost an SOI wafer with high electrical reliability in a device fabrication process, that has an excellent electric property without generation of micro pits by cleaning with hydrofluoric acid etc. even in the case of forming an extremely thin silicon active layer, or that retains high insulation property even in the case of forming an extremely thin inter-layer insulator film.

Abstract: An SOI wafer in which a base wafer and a bond wafer respectively consisting of silicon single crystal are bonded via an oxide film, and then the bond wafer is thinned to form a silicon active layer, wherein the base wafer is formed of silicon single crystal grown by Czochralski method, and the whole surface of the base wafer is within N region outside OSF region and doesn't include a defect region detected by Cu deposition method, or the whole surface of the base wafer is within a region outside OSF region, doesn't include a defect region detected by Cu deposition method, and includes I region containing dislocation cluster due to interstitial silicon. Thereby, there is provided an SOI wafer that retains high insulating properties and has an excellent electrical reliability in device fabrication even in the case of forming an extremely thin interlevel dielectric oxide film with, for example, a thickness of 100 nm or less.

Abstract: The present invention is a method for producing a single crystal with pulling the single crystal from a raw material melt in a chamber by CZ method, wherein when growing the single crystal, where a pulling rate is defined as V and a temperature gradient of the crystal is defined as G during growing the single crystal, the temperature gradient G of the crystal is controlled by changing at least two or more of pulling conditions. Thereby, there is provided a method for producing a single crystal in which when the single crystal is grown by CZ method, V/G can be controlled without lowering a pulling rate V, and thus the single crystal including a desired defect region can be produced effectively for a short time.

Abstract: The present invention is an apparatus for producing a single crystal by which a silicon single crystal is grown by Czochralski method, comprising, at least, a gas flow-guide cylinder which is disposed so as to surround the silicon single crystal in a chamber for growing the single crystal in order to straighten flow of a gas introduced into the chamber, and a quartz member containing bubbles that is provided inside the gas flow-guide cylinder. Thereby, there can be provided a single crystal-producing apparatus by which when a CZ silicon single crystal is grown, a silicon single crystal having a desired defect region being uniform in a plane can be effectively produced by controlling F/G along the radial direction in the single crystal plane constantly to be a predetermined value, and further contamination with impurities of Fe and Cu is prevented, and thereby a silicon single crystal of high quality can be produced.

Abstract: A method for producing a single crystal in which when the single crystal is grown by Czochralski method, V/G is controlled by controlling a fluctuation of a temperature gradient G of the crystal which is being pulled without lowering a pulling rate V, thereby the single crystal including a desired defect region over a whole plane in a radial direction of the crystal entirely in a direction of the crystal growth axis can be produced effectively for a short time at a high yield.

Abstract: The present invention provides an annealed wafer which has a wafer surface layer serving as a device fabricating region and having an excellent oxide film dielectric breakdown characteristic, and a wafer bulk layer in which oxide precipitates are present at a high density at the stage before the wafer is loaded into the device fabrication processes to give an excellent IG capability, and a method for manufacturing the annealed wafer. The present invention is directed to an annealed wafer obtained by performing heat treatment on a silicon wafer manufactured from a silicon single crystal grown by the Czochralski method, wherein a good chip yield of an oxide film dielectric breakdown characteristic in a region having at least a depth of up to 5 ?m from a wafer surface is 95% or more, and a density of oxide precipitates detectable in the wafer bulk and each having a size not smaller than a size showing a gettering capability is not less than 1×109/cm3.

Abstract: In a method for producing a silicon single crystal by Czochralski method, the single crystal is grown with controlling a growth rate between a growth rate at a boundary where a defect region detected by Cu deposition remaining after disappearance of OSF ring disappears when gradually decreasing a growth rate of silicon single crystal during pulling and a growth rate at a boundary where a high oxygen precipitation Nv region having a density of BMDs of 1×107 numbers/cm3 or more and/or a wafer lifetime of 30 ?sec or less after oxygen precipitation treatment disappears when gradually decreasing the growth rate further. Thereby, there is provided a silicon single crystal which does not belong to any of V region rich in vacancy, OSF region and I region rich in interstitial silicon, and has excellent electrical characteristics and gettering capability, so that yield of devices can be surely improved, and also an epitaxial wafer.