Abstract: A solid-state image-capturing device which has built in an image-capturing area including a light receiving element provided on a semiconductor substrate, a substrate bias circuit, and a clamp circuit for receiving output of the substrate bias circuit and applying the output of the substrate bias circuit to the semiconductor substrate in accordance with a substrate pulse, comprises a substrate bias control circuit for controlling so as to reduce an electric current of the clamp circuit during a predetermined period.

Abstract: A drive circuit applying two or more drive voltages to a charge transfer unit includes at least one current mirror circuit that receives a reference current and outputs a predetermined current; at least one switch circuit that switches the current output from the at least one current mirror circuit to apply the multiple drive voltages to the charge transfer unit; and at least one time constant circuit that gives a predetermined time constant to the reference current in the switching by the switch circuit.

Abstract: When a signal is read from a CCD solid-state image pickup element, the CCD solid-state image pickup element is driven with at least two driving voltages so that high-speed reading is performed with generation of noise due to interference between the driving voltages reduced. The CCD solid-state image includes a charge storage section between a vertical transfer register and a horizontal transfer register. By performing the transfer of charge in the direction of columns during an effective transfer period of the transfer in the direction of rows, signal charge of one row generated by a light receiving sensor is transferred to the charge storage section, and by performing the transfer outside the effective transfer period in the transfer in the direction of the row, the signal charge of one row transferred to the charge storage section is transferred to the horizontal transfer register.

Abstract: A transconductance-adjusting circuit includes a first VI converting circuit for converting a first reference voltage which is input to a current; a resistor for producing a voltage from the current output from the first VI converting circuit; a second VI converting circuit for outputting a current corresponding to a potential difference between the voltage produced by the resistor and a second reference voltage; an IV converting circuit for converting the current output from the second VI converting circuit to a voltage; and a feedback unit for changing operating points of an input circuit for inputting the first reference voltage of the first VI converting circuit by the voltage output from the IV converting circuit so that the potential difference is 0. The voltage output from the IV converting circuit is provided to a bias source for an input differential pair in a primary RC filter.

Abstract: A transconductance-adjusting circuit includes a first VI converting circuit for converting a first reference voltage which is input to a current; a resistor for producing a voltage from the current output from the first VI converting circuit; a second VI converting circuit for outputting a current corresponding to a potential difference between the voltage produced by the resistor and a second reference voltage; an IV converting circuit for converting the current output from the second VI converting circuit to a voltage; and a feedback unit for changing operating points of an input circuit for inputting the first reference voltage of the first VI converting circuit by the voltage output from the IV converting circuit so that the potential difference is 0. The voltage output from the IV converting circuit is provided to a bias source for an input differential pair in a primary RC filter.

Abstract: A method of manufacturing a semiconductor integrated circuit device having a plurality of chips mounted thereon, the semiconductor integrated circuit device being fabricated as a package. This manufacturing method comprises a process for mounting a plurality of chips containing a chip 101 including a characteristic adjustment means 7 and a chip 102 which does not include the characteristic adjustment means 7 and fabricating these chips as a package to form a semiconductor integrated circuit device 1 and a succeeding process for adjusting a characteristic of the chip 101 including the characteristic adjustment means 7 and a characteristic of the chip 102 which does not include the characteristic adjustment means 7 by using the characteristic adjustment means 7. A method of manufacturing a semiconductor integrated circuit device according to the present invention can make an analog characteristic become high in accuracy as a product specification and which can reduce a time required by an inspection process.

Abstract: A switched capacitor amplifier useful in integrated circuits and capable of low power operation, wherein the amplifier comprises at least one first hold capacitor, at least one second hold capacitor, a transconductance amplifier, first switching circuit for either (a) allowing the first hold capacitor to retain an input voltage, or (b) outputting retained input voltage through the transconductance amplifier, and a second switching circuit for either (a) feeding a voltage obtained by reversing the polarity of voltage retained by the second hold capacitor back to the transconductance amplifier for outputting as output voltage, or (b) allowing voltage retained by the first hold capacitor to be held by the second hold capacitor.