Patents by Inventor Masahiro Seiki

Masahiro Seiki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6873174
    Abstract: A first signal line and a second signal line are paired, and in one signal line selection period, CPU of the inspection circuit controls a write circuit and writes analog signals into the first signal line selected by means of a switch of the selection circuit. In the next signal line selection period, CPU controls a read circuit and reads output signals from the second signal line selected by means of the switch. CPU detects a short circuit between the paired signal lines based upon the output signals from the second signal line.
    Type: Grant
    Filed: January 4, 2001
    Date of Patent: March 29, 2005
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Ikuo Matsunaga, Ryoichi Watanabe, Masahiro Seiki
  • Patent number: 6839109
    Abstract: There is provided a liquid crystal display wherein a first display region corresponding to a first area on which first pixel electrodes are provided displays an image by light reflection mode, and a second display region corresponding to a second area on which second pixel electrodes are provided can display an image by light transmission mode.
    Type: Grant
    Filed: January 6, 2004
    Date of Patent: January 4, 2005
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Masahiro Seiki, Ryoichi Watanabe, Akimasa Toyama
  • Publication number: 20040135948
    Abstract: There is provided a liquid crystal display wherein a first display region corresponding to a first area on which first pixel electrodes are provided displays an image by light reflection mode, and a second display region corresponding to a second area on which second pixel electrodes are provided can display an image by light transmission mode.
    Type: Application
    Filed: January 6, 2004
    Publication date: July 15, 2004
    Inventors: Masahiro Seiki, Ryoichi Watanabe, Akimasa Toyama
  • Patent number: 6714270
    Abstract: There is provided a liquid crystal display wherein a first display region corresponding to a first area on which first pixel electrodes are provided displays an image by light reflection mode, and a second display region corresponding to a second area on which second pixel electrodes are provided can display an image by light transmission mode.
    Type: Grant
    Filed: January 14, 2002
    Date of Patent: March 30, 2004
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Masahiro Seiki, Ryoichi Watanabe, Akimasa Toyama
  • Publication number: 20030184334
    Abstract: A first signal line and a second signal line are paired, and in one signal line selection period, CPU of the inspection circuit controls a write circuit and writes analog signals into the first signal line selected by means of a switch of the selection circuit. In the next signal line selection period, CPU controls a read circuit and reads output signals from the second signal line selected by means of the switch. CPU detects a short circuit between the paired signal lines based upon the output signals from the second signal line.
    Type: Application
    Filed: January 4, 2001
    Publication date: October 2, 2003
    Inventors: Ikuo Matsunaga, Ryoichi Watanabe, Masahiro Seiki
  • Publication number: 20020126240
    Abstract: There is provided a liquid crystal display wherein a first display region corresponding to a first area on which first pixel electrodes are provided displays an image by light reflection mode, and a second display region corresponding to a second area on which second pixel electrodes are provided can display an image by light transmission mode.
    Type: Application
    Filed: January 14, 2002
    Publication date: September 12, 2002
    Inventors: Masahiro Seiki, Ryoichi Watanabe, Akimasa Toyama
  • Patent number: 6235561
    Abstract: An array substrate of a liquid crystal display device has a glass substrate on which gate lines, signal lines, pixel electrodes, and thin-film transistors are arranged. Each of the thin-film transistors includes a gate electrode composed of a part of one of the gate lines and including a first conductive layer formed on the glass substrate and a second conductive layer covering the first conductive layer. A gate insulating film is formed on the glass substrate and covers the gate electrode. A thin non-single-crystal silicon film is disposed on the gate insulating film on the gate electrode and includes a channel region. Source and drain electrodes are connected electrically to the thin non-single-crystal silicon film.
    Type: Grant
    Filed: July 13, 1998
    Date of Patent: May 22, 2001
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Masahiro Seiki, Akira Kubo
  • Patent number: 5811835
    Abstract: An array substrate of a liquid crystal display device has a glass substrate on which gate lines, signal lines, pixel electrodes, and thin-film transistors are arranged. Each of the thin-film transistors includes a gate electrode composed of a part of one of the gate lines and including a first conductive layer formed on the glass substrate and a second conductive layer covering the first conductive layer. A gate insulating film is formed on the glass substrate and covers the gate electrode. A thin non-single-crystal silicon film is disposed on the gate insulating film on the gate electrode and includes a channel region. Source and drain electrodes are connected electrically to the thin non-single-crystal silicon film. The first conductive layer has two opposite side edge portions extending inclined at an angle to the surface of the substrate, the inclination angle of each side edge portion is ranges from 10.degree. to 30.degree.
    Type: Grant
    Filed: August 22, 1996
    Date of Patent: September 22, 1998
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Masahiro Seiki, Akira Kubo
  • Patent number: 5811846
    Abstract: In a thin-film transistor 171, in order to sufficiently suppress an optical leakage current Ioff, thereby achieving a high ON/OFF current ratio, at least one of shortest distances between an arbitrary intersection of an outline of a gate electrode 131 and an outline of a drain electrode 141 and an intersection of the outline of the gate electrode 131 and an outline of a source electrode 151 is formed to be larger than the shortest distance between a portion of the outline of the gate electrode 131 overlapping the drain electrode 141 and another portion thereof overlapping the source electrode 151.
    Type: Grant
    Filed: July 3, 1996
    Date of Patent: September 22, 1998
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yasunori Miura, Makoto Shibusawa, Atsushi Sugahara, Masahiro Seiki
  • Patent number: 5784135
    Abstract: An object of the technology of our invention is to solve a luminance defect viewed as a "seam" or the like and to provide a liquid crystal display device having a screen for equally displaying an image. For example, when an exposing process is performed for one conductor layer or a dielectric layer, a total of four photomasks are used corresponding to four shot areas. A light insulation layer of a photomask used for the exposing process for patterning for example a signal line is formed so that it becomes a projection pattern of the signal line. The photomasks corresponding to adjacent shot areas are formed so that patterns of the light insulation layers of the boundary portion are engaged with each other on the plane.
    Type: Grant
    Filed: October 3, 1996
    Date of Patent: July 21, 1998
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Katsuhiko Inada, Osamu Shimada, Masahiro Seiki, Ryuji Tada, Atsushi Sugahara
  • Patent number: 5656526
    Abstract: An object of the technology of our invention is to solve a luminance defect viewed as a "seam" or the like and to provide a liquid crystal display device having a screen for equally displaying an image. For example, when an exposing process is performed for one conductor layer or a dielectric layer, a total of four photomasks are used corresponding to four shot areas. A light insulation layer of a photomask used for the exposing process for patterning for example a signal line is formed so that it becomes a projection pattern of the signal line. The photomasks corresponding to adjacent shot areas are formed so that patterns of the light insulation layers of the boundary portion are engaged with each other on the plane.
    Type: Grant
    Filed: November 7, 1995
    Date of Patent: August 12, 1997
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Katsuhiko Inada, Osamu Shimada, Masahiro Seiki, Ryuji Tada, Atsushi Sugahara
  • Patent number: 5563432
    Abstract: In a thin-film transistor 171, in order to sufficiently suppress an optical leakage current Ioff, thereby achieving a high ON/OFF current ratio, at least one of shortest distances between an arbitrary intersection of an outline of a gate electrode 131 and an outline of a drain electrode 141 and an intersection of the outline of the gate electrode 131 and an outline of a source electrode 151 is formed to be larger than the shortest distance between a portion of the outline of the gate electrode 131 overlapping the drain electrode 141 and another portion thereof overlapping the source electrode 151.
    Type: Grant
    Filed: December 23, 1994
    Date of Patent: October 8, 1996
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yasunori Miura, Makoto Shibusawa, Atsushi Sugahara, Masahiro Seiki