Patents by Inventor Masahiro Shiina
Masahiro Shiina has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 6967406Abstract: A layout method of a semiconductor integrated circuit is provided which improves characteristics of the circuit by giving hierarchical structure of interconnections regularity. A pair of emitter followers is disposed symmetrically with respect to a center line of a differential amplifier. Thus, interconnections within a circuit block and a ground wiring can be made with a single metal layer, since an area where the interconnections cross with each other is eliminated. Herewith cross talk due to the intersection of the interconnections can be resolved. Also, the interconnections between the differential amplifier and the emitter follower circuits can be made equal in length. It is possible to assign a second metal layer to interconnections between circuit blocks and a third metal layer to a power supply so that characteristics of the semiconductor integrated circuit are improved.Type: GrantFiled: October 23, 2002Date of Patent: November 22, 2005Assignee: Sanyo Electric Co., Ltd.Inventor: Masahiro Shiina
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Patent number: 6888378Abstract: This invention prevents a cross talk caused by intersection of interconnections, and offers a semiconductor integrated circuit with improved circuit characteristics. By disposing a pair of emitter follower circuits symmetrically with respect to a center line of a differential amplifier, an area where the interconnections cross with each other is eliminated and interconnections within a circuit block and a ground wiring can be made with a single metal layer. Herewith cross talk due to the intersection of the interconnections can be resolved.Type: GrantFiled: October 23, 2002Date of Patent: May 3, 2005Assignee: Sanyo Electric Co., Ltd.Inventor: Masahiro Shiina
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Patent number: 6730985Abstract: Unnecessary crossing of interconnections are eliminated to reduce the impedance of wiring of an LSI of a semiconductor integrated circuit device. In the semiconductor integrated circuit device of multi layer structure having a circuit block, a pad electrically connected with the circuit block and a protection circuit electrically connected with the pad, a plurality of cells each including the pad and the protection circuit disposed adjacent to each other are disposed along a periphery of the circuit block. Impedance of the wiring in the LSI is reduced by disposing a top metal layer providing a power supply voltage Vcc along outer sides of the cells and by making the width of a bottom metal layer providing a ground voltage, or a reference voltage, as wide as possible.Type: GrantFiled: March 28, 2003Date of Patent: May 4, 2004Assignee: Sanyo Electric Co., Ltd.Inventor: Masahiro Shiina
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Publication number: 20040036120Abstract: Influence of signal noise among circuits formed on a semiconductor device is suppressed. When the noise occurs in a circuit block in the semiconductor device of a stacked configuration having a plurality of circuit blocks, the influence of signal noise on the other circuit blocks is suppressed by forming a box mostly made of metal over the circuit block which generates the noises.Type: ApplicationFiled: June 26, 2003Publication date: February 26, 2004Applicant: Sanyo Electric Co., Ltd.Inventor: Masahiro Shiina
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Publication number: 20040012065Abstract: Unnecessary crossing of interconnections are eliminated to reduce impedance of LSI wiring in a semiconductor integrated circuit device. The semiconductor integrated circuit device includes a circuit block having many elements such as resistances, transistors and capacitors. Pad electrically connected with the circuit blocks and protection circuits electrically connected with the pads are aligned along a periphery of the circuit block. Impedance of the wiring in the LSI is reduced by disposing a top layer metal providing a power supply voltage Vcc along outer sides of the aligned pads and protection circuits, and by disposing a bottom layer metal providing ground voltage as wide as possible over the entire space between the circuit block and the aligned pads and protection circuits.Type: ApplicationFiled: May 28, 2003Publication date: January 22, 2004Applicant: Sanyo Electric Co., Ltd.Inventor: Masahiro Shiina
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Publication number: 20030222274Abstract: Unnecessary crossing of interconnections are eliminated to reduce the impedance of wiring of an LSI of a semiconductor integrated circuit device. In the semiconductor integrated circuit device, of multi layer structure having a circuit block, a pad electrically connected with the circuit block and a protection circuit electrically connected with the pad, a plurality of cells each including the pad and the protection circuit disposed adjacent to each other are disposed along a periphery of the circuit block. Impedance of the wiring in the LSI is reduced by disposing a top metal layer providing a power supply voltage Vcc along outer sides of the cells and by making the width of a bottom metal layer providing a ground voltage, or a reference voltage, as wide as possible.Type: ApplicationFiled: March 28, 2003Publication date: December 4, 2003Inventor: Masahiro Shiina
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Publication number: 20030111673Abstract: Desired circuit characteristics are obtained by realizing a layout considering symmetry of semiconductor elements in a circuit block. Emitter follower circuits are disposed close to a differential amplifier and symmetrically with respect to a center line of the differential amplifier. Bipolar transistors in the emitter follower circuits are disposed close to bipolar transistors in the differential amplifier with difference in orientation by 90 degrees or 270 degrees. Hereby symmetry of the differential amplifier in the emitter follower circuits is improved to have better circuit characteristics, as the interconnections from the differential amplifier to the emitter follower circuits are kept from intersecting with each other and can be made equal in length.Type: ApplicationFiled: November 12, 2002Publication date: June 19, 2003Inventor: Masahiro Shiina
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Publication number: 20030075736Abstract: A layout method of a semiconductor integrated circuit is provided which improves characteristics of the circuit by giving hierarchical structure of interconnections regularity. A pair of emitter followers is disposed symmetrically with respect to a center line of a differential amplifier. Thus, interconnections within a circuit block and a ground wiring can be made with a single metal layer, since an area where the interconnections cross with each other is eliminated. Herewith cross talk due to the intersection of the interconnections can be resolved. Also, the interconnections between the differential amplifier and the emitter follower circuits can be made equal in length. It is possible to assign a second metal layer to interconnections between circuit blocks and a third metal layer to a power supply so that characteristics of the semiconductor integrated circuit are improved.Type: ApplicationFiled: October 23, 2002Publication date: April 24, 2003Inventor: Masahiro Shiina
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Publication number: 20030075771Abstract: This invention prevents a cross talk caused by intersection of interconnections, and offers a semiconductor integrated circuit with improved circuit characteristics. By disposing a pair of emitter follower circuits symmetrically with respect to a center line of a differential amplifier, an area where the interconnections cross with each other is eliminated and interconnections within a circuit block and a ground wiring can be made with a single metal layer. Herewith cross talk due to the intersection of the interconnections can be resolved.Type: ApplicationFiled: October 23, 2002Publication date: April 24, 2003Inventor: Masahiro Shiina
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Patent number: 5757467Abstract: When negative images on a negative film are stored in a negative image storing unit, an index print image is constructed by an index constructing section in an image processing unit on the basis of the inputted images, which is displayed as a positive image on a monitor through a display instructing section. Images having different top-to-bottom directions in each of lateral and vertical image groups are indicated by key operation on a keyboard connected to the image processing unit with respect to the index print image displayed on the monitor. The direction of the indicated image is changed by a direction changing section in the image processing unit, and then the image is displayed on the monitor again. An index print image after changing the direction is displayed in an index printing section (on a liquid crystal panel). Thus an index print is prepared.Type: GrantFiled: July 25, 1996Date of Patent: May 26, 1998Assignee: Fuji Photo Film Co., Ltd.Inventors: Kazuhiko Katakura, Hiroaki Nakamura, Masahiro Shiina