Abstract: There is provided an EEPROM semiconductor device including (a) a plurality of field insulating films each extending perpendicularly to word lines, (b) a plurality of memory cells arranged in a matrix, each memory cell having a floating gate, a control gate formed on the floating gate and doubling as a word line, and source and drain regions located at either sides of the control gate, (c) a common source line extending in parallel with the word lines and connecting source regions of the memory cells with each other, and (d) a first bit line extending perpendicularly to the word lines and connecting drain regions of the memory cells with each other. The above-mentioned EEPROM semiconductor device makes it possible to form CMOS logic circuit together with a non-volatile memory on a common semiconductor substrate without increasing fabrication steps, and also makes it possible for the non-volatile memory to write data thereinto and read data therefrom at a higher rate without an increase in a cell size.

Abstract: The semiconductor device with its primary bit line and secondary bit lines, according to the present invention, is capable of being accessed at a high speed. In this semiconductor device, any one of a plurality of secondary bit lines is selectively connected to the primary bit line. The primary bit line 1 and secondary bit lines 3 are all formed on the same insulating film 26. A lined layer of wiring 15 for a memory cell selection word line 8 is formed on an insulating film 27.

Abstract: There is provided an EEPROM semiconductor device including (a) a plurality of field insulating films each extending perpendicularly to word lines, (b) a plurality of memory cells arranged in a matrix, each memory cell having a floating gate, a control gate formed on the floating gate and doubling as a word line, and source and drain regions located at either sides of the control gate, (c) a common source line extending in parallel with the word lines and connecting source regions of the memory cells with each other, and (d) a first bit line extending perpendicularly to the word lines and connecting drain regions of the memory cells with each other. The above-mentioned EEPROM semiconductor device makes it possible to form CMOS logic circuit together with a non-volatile memory on a common semiconductor substrate without increasing fabrication steps, and also makes it possible for the non-volatile memory to write data thereinto and read data therefrom at a higher rate without an increase in a cell size.

Abstract: There is provided an EEPROM semiconductor device including (a) a plurality of field insulating films each extending perpendicularly to word lines, (b) a plurality of memory cells arranged in a matrix, each memory cell having a floating gate, a control gate formed on the floating gate and doubling as a word line, and source and drain regions located at either sides of the control gate, (c) a common source line extending in parallel with the word lines and connecting source regions of the memory cells with each other, and (d) a first bit line extending perpendicularly to the word lines and connecting drain regions of the memory cells with each other. The above-mentioned EEPROM semiconductor device makes it possible to form CMOS logic circuit together with a non-volatile memory on a common semiconductor substrate without increasing fabrication steps, and also makes it possible for the non-volatile memory to write data thereinto and read data therefrom at a higher rate without an increase in a cell size.

Abstract: An electrically erasable and programmable read only memory device includes a plurality of memory cells, each of which has a drain region, a source region, and a programming region, a first gate insulating film covering a part of the drain region, a second gate insulating film covering a part of the programming region, and a floating gate having a first portion overlapping the first gate insulating film to form a first capacitance therebetween and a second portion overlapping the second gate insulating film to form a second capacitance. The first capacitance is designed to be larger than the second capacitance, so that the injection and extraction of carriers take place between the programming region and the floating gate.

Abstract: An electrically erasable and programmable read only memory device includes a plurality of memory cells, each of which has a drain region, a source region, and a programming region, a first gate insulating film covering a part of the drain region, a second gate insulating film covering a part of the programming region, and a floating gate having a first portion overlapping the first gate insulating film to form a first capacitance therebetween and a second portion overlapping the second gate insulating film to form a second capacitance. The first capacitance is designed to be larger than the second capacitance, so that the injection and extraction of carriers take place between the programming region and the floating gate.