Patents by Inventor Masahiro Shiota

Masahiro Shiota has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11158658
    Abstract: [Object] To achieve a radiation detector capable of suppressing variation in the amount of radiation detected. [Solution] A first gate electrode (52) is connected to a light receiving device, and a second gate electrode (53) is configured to have the same potential as that of the first gate electrode (52).
    Type: Grant
    Filed: June 10, 2019
    Date of Patent: October 26, 2021
    Assignee: SHARP KABUSHIKI KAISHA
    Inventors: Masahiro Shiota, Shigenari Taguchi, Takahiro Shindoh, Kunihiko Iizuka, Nobuyuki Ashida
  • Patent number: 10886314
    Abstract: [Object] To achieve a high-sensitivity radiation detector. [Solution] An amplifying transistor (3) is configured such that a photodiode (1) receives light with the amplifying transistor (3) conductive.
    Type: Grant
    Filed: June 14, 2019
    Date of Patent: January 5, 2021
    Assignee: SHARP KABUSHIKI KAISHA
    Inventors: Masahiro Shiota, Shigenari Taguchi, Takahiro Shindoh, Kunihiko Iizuka, Nobuyuki Ashida
  • Publication number: 20200213552
    Abstract: [Object] To reduce 1/f noise by utilizing the functionality of controlling row selection, with which a typical solid-state imaging element is provided. [Solution] A solid-state imaging element (1A) includes a pixel array (A) in which a plurality of columns of pixels (P) are arranged, a row selection unit (13) that specifies a readout row of the pixel array (A), and a control device (30) that sweeps information carried by each pixel (P) a plurality of times by controlling the row selection unit (13) and outputs an output value in accordance with results of a plurality of readouts of the information obtained from each pixel (P) by the sweeping.
    Type: Application
    Filed: December 23, 2019
    Publication date: July 2, 2020
    Inventors: NOBUYUKI ASHIDA, KUNIHIKO IIZUKA, SHIGENARI TAGUCHI, MASAHIRO SHIOTA
  • Publication number: 20200014863
    Abstract: [Object] To realize an image capturing apparatus capable of suppressing noise in an image. [Solution] An image capturing apparatus (100) includes a plurality of pixels (110) arranged in a matrix form. Each pixel includes a switching element (112) configured to control outputting of a charge accumulated in a sensor element (111). Pixels in each column are grouped into blocks (120). Each block includes a block switching element (122) configured to control outputting.
    Type: Application
    Filed: July 3, 2019
    Publication date: January 9, 2020
    Inventors: MASAHIRO SHIOTA, SHIGENARI TAGUCHI, KUNIHIKO IIZUKA, NOBUYUKI ASHIDA
  • Publication number: 20190386046
    Abstract: [Object] To achieve a high-sensitivity radiation detector. [Solution] An amplifying transistor (3) is configured such that a photodiode (1) receives light with the amplifying transistor (3) conductive.
    Type: Application
    Filed: June 14, 2019
    Publication date: December 19, 2019
    Inventors: MASAHIRO SHIOTA, SHIGENARI TAGUCHI, TAKAHIRO SHINDOH, KUNIHIKO IIZUKA, NOBUYUKI ASHIDA
  • Publication number: 20190386045
    Abstract: [Object] To achieve a radiation detector capable of suppressing variation in the amount of radiation detected. [Solution] A first gate electrode (52) is connected to a light receiving device, and a second gate electrode (53) is configured to have the same potential as that of the first gate electrode (52).
    Type: Application
    Filed: June 10, 2019
    Publication date: December 19, 2019
    Inventors: MASAHIRO SHIOTA, SHIGENARI TAGUCHI, TAKAHIRO SHINDOH, KUNIHIKO IIZUKA, NOBUYUKI ASHIDA
  • Patent number: 8866153
    Abstract: Provided is a functional element which is obtained by forming a lamination film on a substrate and then dividing the substrate and the lamination film into a desired shape. The functional element has a hexagonal substrate, a lamination film formed on a C surface of the substrate, and a plurality of divided surfaces which are exposed by dividing the substrate into quadrilaterals. At least one line of division lines in the case of dividing the substrate into quadrilaterals is perpendicular to any one of equivalent directions of [1-100], [?1010], and [01-01] of the substrate from a [0001] direction of the substrate, and the divided surfaces formed by the division lines are inclined in a direction of other divided surfaces to which at least a part thereof is opposed.
    Type: Grant
    Filed: January 18, 2011
    Date of Patent: October 21, 2014
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Akihiro Urata, Masahiro Araki, Takaaki Utsumi, Masahiro Shiota
  • Publication number: 20120292642
    Abstract: Provided is a functional element which is obtained by forming a lamination film on a substrate and then dividing the substrate and the lamination film into a desired shape. The functional element has a hexagonal substrate, a lamination film formed on a C surface of the substrate, and a plurality of divided surfaces which are exposed by dividing the substrate into quadrilaterals. At least one line of division lines in the case of dividing the substrate into quadrilaterals is perpendicular to any one of equivalent directions of [1-100], [-1010], and [01-01] of the substrate from a [0001] direction of the substrate, and the divided surfaces formed by the division lines are inclined in a direction of other divided surfaces to which at least a part thereof is opposed.
    Type: Application
    Filed: January 18, 2011
    Publication date: November 22, 2012
    Applicant: Sharp Kabushiki Kaisha
    Inventors: Akihiro Urata, Masahiro Araki, Takaaki Utsumi, Masahiro Shiota
  • Publication number: 20100124420
    Abstract: A communication device and a communication method eliminating clock errors are provided. Clock signals having the same frequency are used for specific consecutive circuits in a communication device in which two or more types of clock signals are used together. Preferably, the specific circuits includes: a reception function unit adapted to receive and transmit specific signals; an MPCP function unit adapted to output MPCP frames after assigning LLIDs for identifying ONUs; a signal selection unit adapted to convert an output signal from the reception function unit and an output signal from the MPCP function unit into a single output signal; a branch function unit adapted to branch the specific signals; and a first and second transmission function unit adapted to transmit the specific signals.
    Type: Application
    Filed: November 19, 2009
    Publication date: May 20, 2010
    Inventor: MASAHIRO SHIOTA
  • Patent number: 6599834
    Abstract: A process of manufacturing a semiconductor device including the steps of: filling a photoresist in a concave portion provided on a surface of a semiconductor substrate; forming a power-feeding thin metal film for electrolytic plating on the semiconductor substrate including a surface of the thus filled photoresist; and forming wiring on the power-feeding thin metal film in a region not above the concave portion by electrolytic plating.
    Type: Grant
    Filed: May 28, 2002
    Date of Patent: July 29, 2003
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Toshiyuki Nakashima, Masahiro Shiota
  • Publication number: 20020177305
    Abstract: A process of manufacturing a semiconductor device including the steps of: filling a photoresist in a concave portion provided on a surface of a semiconductor substrate; forming a power-feeding thin metal film for electrolytic plating on the semiconductor substrate including a surface of the thus filled photoresist; and forming wiring on the power-feeding thin metal film in a region not above the concave portion by electrolytic plating.
    Type: Application
    Filed: May 28, 2002
    Publication date: November 28, 2002
    Inventors: Toshiyuki Nakashima, Masahiro Shiota
  • Patent number: 6410945
    Abstract: A heterojunction bipolar transistor having a ballast resistance layer between an AlGaAs emitter layer and an emitter electrode, wherein the ballast resistance layer comprises n-AlxGa1−XAs, wherein 0<X<1, and a GaAs selective etching layer is provided between the emitter layer and the ballast resistance layer.
    Type: Grant
    Filed: June 23, 2000
    Date of Patent: June 25, 2002
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Masahiro Shiota, Toshiyuki Shinozaki, Hideyuki Tsuji, Toshiaki Kinosada