Patents by Inventor Masahiro Sugawara

Masahiro Sugawara has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11927218
    Abstract: A sealing device is disposed between an inner member and an outer member that rotate relative to each other to seal a gap between the inner member and the outer member of the sealing device, and includes a first sealing member including a cylindrical part to be mounted to the outer member, and an annular part that extends radially inward from the cylindrical part toward the inner member; and a second sealing member including a sleeve to be mounted to the inner member, and a flange that extends radially outward from the sleeve, the flange facing the annular part of the first sealing member. The first sealing member includes at least three axial lips made from an elastic material that extends from the annular part toward the flange of the second sealing member. An axial lip disposed radially outer side has an interference that is greater than that of an axial lip disposed radially inner side.
    Type: Grant
    Filed: November 5, 2019
    Date of Patent: March 12, 2024
    Assignee: NOK CORPORATION
    Inventors: Shintaro Sugawara, Masahiro Seki, Yuichi Tarukawa
  • Patent number: 10452767
    Abstract: A semiconductor system according to the present disclosure includes: an input receiving unit that receives comparison process requesting information; a processing unit that acquires a plurality of pieces of process related information related to a semiconductor process performed by a semiconductor manufacturing apparatus, based on the comparison process requesting information received by the input receiving unit; a screen creation unit that creates a comparison screen for comparing the plurality of pieces of process related information acquired by the processing unit; and a display unit that displays the comparison screen created by the screen creation unit.
    Type: Grant
    Filed: October 12, 2017
    Date of Patent: October 22, 2019
    Assignee: Tokyo Electron Limited
    Inventors: Masahiro Sugawara, Yojiro Aoki
  • Publication number: 20180107637
    Abstract: A semiconductor system according to the present disclosure includes: an input receiving unit that receives comparison process requesting information; a processing unit that acquires a plurality of pieces of process related information related to a semiconductor process performed by a semiconductor manufacturing apparatus, based on the comparison process requesting information received by the input receiving unit; a screen creation unit that creates a comparison screen for comparing the plurality of pieces of process related information acquired by the processing unit; and a display unit that displays the comparison screen created by the screen creation unit.
    Type: Application
    Filed: October 12, 2017
    Publication date: April 19, 2018
    Inventors: Masahiro Sugawara, Yojiro Aoki
  • Publication number: 20140170245
    Abstract: Provided is an inorganic composite compound having reduced oxygen and a high reducing ability, which includes elements having a positive atomic valence of a plant-derived component and a sulfur compound. The compound provides a therapeutic treatment effect and a pharmacological effect and is useful to suppress the influence of active oxygen (oxidization) and cannot be produced by a synthetic chemical technique.
    Type: Application
    Filed: June 29, 2012
    Publication date: June 19, 2014
    Inventors: Eiki Nakayama, Masahiro Sugawara
  • Patent number: 6514345
    Abstract: A semiconductor manufacturing apparatus is improved so that apparatus operating condition parameters can be restored to setting values of various levels such as standard, apparatus delivery time or client oriented setting values even if the parameters are overwritten. The semiconductor manufacturing apparatus is constituted by a multi-chamber processing system 4, a transport system 8 of an object and an equipment control unit 210 having a memory apparatus 214 storing the apparatus operating condition parameters and providing the parameters to machine control units 150, 72. The machine control units 150, 72 controls the processing system 4 and the transport system 8 based on the apparatus operating condition parameters.
    Type: Grant
    Filed: September 21, 2000
    Date of Patent: February 4, 2003
    Assignee: Tokyo Electron Limited
    Inventors: Masaya Nagata, Masahiro Sugawara
  • Patent number: 6171916
    Abstract: A semiconductor device in which a salicide structure is applied to a buried gate transistor to largely reduce a difference of level or height in a element and to reduce the resistance of a gate electrode and a source/drain structure, thus enabling reliable high speed operations while maintaining high performance. For manufacturing the semiconductor device, a silicon substrate is formed with a groove for a buried gate. A gate insulating film is formed on the bottom surface of the groove. Then, side-wall insulating films are formed on both side surfaces of the groove in a large thickness as compared with that of the gate insulating film. Next, after a gate electrode is formed from a polycrystalline silicon film, a source/drain structure is formed in the silicon substrate through the gate electrode and the side-wall insulating film. Then, a Ti film is formed and annealed to form silicide layers on the gate electrode and on the source/drain electrodes, thus completing a salicide structure.
    Type: Grant
    Filed: October 26, 1999
    Date of Patent: January 9, 2001
    Assignee: Nippon Steel Corporation
    Inventors: Masahiro Sugawara, Katsuki Hazama
  • Patent number: 5994736
    Abstract: A semiconductor device in which a salicide structure is applied to a buried gate transistor to largely reduce a difference of level or height in a element and to reduce the resistance of a gate electrode and a source/drain structure, thus enabling reliable high speed operations while maintaining high performance. For manufacturing the semiconductor device, a silicon substrate is formed with a groove for a buried gate. A gate insulating film is formed on the bottom surface of the groove. Then, side-wall insulating films are formed on both side surfaces of the groove in a large thickness as compared with that of the gate insulating film. Next, after a gate electrode is formed from a polycrystalline silicon film, a source/drain structure is formed in the silicon substrate through the gate electrode and the side-wall insulating film. Then, a Ti film is formed and annealed to form silicide layers on the gate electrode and on the source/drain electrodes, thus completing a salicide structure.
    Type: Grant
    Filed: August 14, 1998
    Date of Patent: November 30, 1999
    Assignee: United Microelectronics Corporation
    Inventors: Masahiro Sugawara, Katsuki Hazama