Patents by Inventor Masahiro Takenaka

Masahiro Takenaka has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11772868
    Abstract: To provide a pouch for achieving a reduced storage space with a simple configuration and a method for manufacturing the pouch. A pouch (10) including a gusset portion (22) includes a pouch main body (20) and an inner supporting member (70) disposed inside the pouch main body (20). The pouch main body (20) includes a content containing portion (21) and a first fixture portion (24) and a second fixture portion (25) that face each other across the content containing portion (21). The inner supporting member (70) includes a first fixing portion (71) fixed to the first fixture portion (24) and a second fixing portion (72) fixed to the second fixture portion (25).
    Type: Grant
    Filed: August 10, 2021
    Date of Patent: October 3, 2023
    Assignee: TOYO SEIKAN CO., LTD.
    Inventors: Hiroki Tanaka, Takahiro Yasuumi, Takahiro Kurosawa, Masahiro Takenaka
  • Publication number: 20210362928
    Abstract: To provide a pouch for achieving a reduced storage space with a simple configuration and a method for manufacturing the pouch. A pouch (10) including a gusset portion (22) includes a pouch main body (20) and an inner supporting member (70) disposed inside the pouch main body (20). The pouch main body (20) includes a content containing portion (21), and a first fixture portion (24) and a second fixture portion (25) that face each other across the content containing portion (21). The inner supporting member (70) includes a first fixing portion (71) fixed to the first fixture portion (24) and a second fixing portion (72) fixed to the second fixture portion (25).
    Type: Application
    Filed: August 10, 2021
    Publication date: November 25, 2021
    Applicant: Toyo Seikan Co., Ltd.
    Inventors: Hiroki Tanaka, Takahiro Yasuumi, Takahiro Kurosawa, Masahiro Takenaka
  • Patent number: 9227771
    Abstract: The purpose of the invention is to provide a very safe opener cap that can easily open a film serving as a section to be opened without scattering the contents. A can body (10) and a screw cap (20) are screwed together, and the screw cap (20) and an opener (30) are ratcheted together so as to rotate as a unit in the direction of the screw cap (20) tightening. Blade angles of an annular blade (34) are configured so that the blade angle in the direction of the screw cap (20) loosing is gentler than the blade angle in the direction of tightening.
    Type: Grant
    Filed: September 20, 2012
    Date of Patent: January 5, 2016
    Assignee: KEY COFFEE INC.
    Inventors: Hiromitsu Ueda, Masahiro Takenaka, You Yamamori, Kazuo Kawamata, Takeshi Sou, Syouzo Fujii
  • Publication number: 20140224801
    Abstract: The purpose of the invention is to provide a very safe opener cap that can easily open a film serving as a section to be opened without scattering the contents. A can body (10) and a screw cap (20) are screwed together, and the screw cap (20) and an opener (30) are ratcheted together so as to rotate as a unit in the direction of the screw cap (20) tightening. Blade angles of an annular blade (34) are configured so that the blade angle in the direction of the screw cap (20) loosing is gentler than the blade angle in the direction of tightening.
    Type: Application
    Filed: September 20, 2012
    Publication date: August 14, 2014
    Applicant: KEY COFFEE INC.
    Inventors: Hiromitsu Ueda, Masahiro Takenaka, You Yamamori, Kazuo Kawamata, Takeshi Sou, Syouzo Fujii
  • Publication number: 20060006412
    Abstract: A semiconductor substrate comprising a silicon substrate with an oxide film on its surface, on which a silicon layer, a warp-relieved SiGe layer and a warped cap layer are formed in this order, a semiconductor device comprising a transistor, a diode, a capacitor and/or a bipolar transistor formed solely or in combination on the above semiconductor substrate and a method of manufacturing the above semiconductor substrate.
    Type: Application
    Filed: September 7, 2005
    Publication date: January 12, 2006
    Applicant: Sharp Kabushiki Kaisha
    Inventors: Masahiro Takenaka, Katsumasa Fujii
  • Patent number: 6927138
    Abstract: Provided is a method of semiconductor device fabrication capable of rounding the sharp edge portions of trenches so as to form device isolation regions having high electrical reliability. A semiconductor substrate comprising a lattice-strain relaxed silicon germanium layer, a silicon germanium layer, and a lattice strained silicon layer formed in this order of mention onto a silicon substrate is used, while trenches are formed in the portions for device isolation regions of the semiconductor substrate by etching. Then, a silicon film is deposited on the entirety of the exposed surface, and the deposited silicon film is dry-oxidized so as to form a silicon dioxide film. As a result, the edge portions of the trenches are rounded.
    Type: Grant
    Filed: October 29, 2003
    Date of Patent: August 9, 2005
    Assignee: Sharp Kabushiki Kaisha
    Inventor: Masahiro Takenaka
  • Patent number: 6869897
    Abstract: The present invention provides a method for manufacturing a semiconductor substrate, comprising the step of: forming a first buffer Si layer on a substrate having a silicon surface; epitaxially growing, in sequence, a first strained SiGe layer and a first Si layer above the first buffer Si layer; implanting ions into the resulting substrate followed by annealing so as to relax the lattice of the first strained SiGe layer and to thereby providing tensile strain in the first Si layer and so that tensile strain is provided in the first Si layer; and epitaxially growing, in sequence, a second buffer Si layer and a second SiGe layer above the resulting substrate; and forming a second Si layer having tensile strain on the second SiGe layer.
    Type: Grant
    Filed: September 5, 2003
    Date of Patent: March 22, 2005
    Assignee: Sharp Kabushiki Kaisha
    Inventor: Masahiro Takenaka
  • Publication number: 20040087107
    Abstract: Provided is a method of semiconductor device fabrication capable of rounding the sharp edge portions of trenches so as to form device isolation regions having high electrical reliability. A semiconductor substrate comprising a lattice-strain relaxed silicon germanium layer, a silicon germanium layer, and a lattice strained silicon layer formed in this order of mention onto a silicon substrate is used, while trenches are formed in the portions for device isolation regions of the semiconductor substrate by etching. Then, a silicon film is deposited on the entirety of the exposed surface, and the deposited silicon film is dry-oxidized so as to form a silicon dioxide film. As a result, the edge portions of the trenches are rounded.
    Type: Application
    Filed: October 29, 2003
    Publication date: May 6, 2004
    Applicant: SHARP KABUSHIKI KAISHA
    Inventor: Masahiro Takenaka
  • Publication number: 20040075106
    Abstract: The present invention provides a method for manufacturing a semiconductor substrate, comprising the step of: forming a first buffer Si layer on a substrate having a silicon surface; epitaxially growing, in sequence, a first strained SiGe layer and a first Si layer above the first buffer Si layer; implanting ions into the resulting substrate followed by annealing so as to relax the lattice of the first strained SiGe layer and to thereby providing tensile strain in the first Si layer and so that tensile strain is provided in the first Si layer; and epitaxially growing, in sequence, a second buffer Si layer and a second SiGe layer above the rezulting substrate; and forming a second Si layer having tensile strain on the second SiGe layer.
    Type: Application
    Filed: September 5, 2003
    Publication date: April 22, 2004
    Applicant: Sharp Kabushiki Kaisha
    Inventor: Masahiro Takenaka
  • Publication number: 20030160300
    Abstract: A semiconductor substrate comprising a silicon substrate with an oxide film on its surface, on which a silicon layer, a warp-relieved SiGe layer and a warped cap layer are formed in this order, a semiconductor device comprising a transistor, a diode, a capacitor and/or a bipolar transistor formed solely or in combination on the above semiconductor substrate and a method of manufacturing the above semiconductor substrate.
    Type: Application
    Filed: February 24, 2003
    Publication date: August 28, 2003
    Inventors: Masahiro Takenaka, Katsumasa Fujii
  • Patent number: 6171897
    Abstract: A method for manufacturing a CMOS semiconductor device having a first conductivity type (1st-type) MOS transistor including a gate electrode made of a 1st-type polysilicon film of high impurity concentration and a second conductivity type (2nd-type) MOS transistor including a gate electrode made of a 2nd-type polysilicon film of high impurity concentration on a single semiconductor substrate, comprising the steps of: forming a polysilicon film on the substrate; forming a first resist mask on the polysilicon film so as to cover a 2nd-type MOS transistor formation region, followed by implanting a 1st-type impurity at a high concentration into the polysilicon film by using the first resist mask; removing the first resist mask; forming a second resist mask on the polysilicon film so as to cover a 1st-type MOS transistor formation region, followed by implanting a 2nd-type impurity at a high concentration into the polysilicon film by using the second resist mask; etching the 2nd-type polysilicon film by a specific
    Type: Grant
    Filed: March 27, 1998
    Date of Patent: January 9, 2001
    Assignee: Sharp Kabushiki Kaisha
    Inventor: Masahiro Takenaka