Patents by Inventor Masahiro TSURUYA

Masahiro TSURUYA has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240054076
    Abstract: A protocol chip writes a request from a host apparatus to a shared memory. One of the plurality of processors reads the request from the host apparatus from the shared memory through an address translation unit and writes a response to the request to the shared memory through the address translation unit. The protocol chip reads the response from the shared memory and sends the response to the host apparatus. In the case where a first processor reboots, the first processor performs a reboot process of a first address translation unit but does not perform the reboot process of the shared memory. A second processor reads a first request addressed to the first processor from the host apparatus through a second address translation unit and writes a first response to the first request to the shared memory through the second address translation unit.
    Type: Application
    Filed: March 6, 2023
    Publication date: February 15, 2024
    Applicant: Hitachi, Ltd.
    Inventors: Kentaro SHIMADA, Nobuhiro Yokoi, Masahiro Tsuruya
  • Patent number: 11853582
    Abstract: A first node receives a read request, determines a storage drive location where data corresponding to one or more logical addresses designated in the read request is stored, and requests transfer of the data at the one or more logical addresses, from the second node, when the storage drive location is the second node. The second node reads a data chunk containing the data designated by the one or more logical addresses, from one or more storage drives, determines whether to decompress the data chunk based on the size of the data chunk and the size of the one or more logical addresses, decompresses the data chunk based on the determination as to decompress the data chunk, extracts data at the one or more logical addresses, and transfers the extracted data to the first node.
    Type: Grant
    Filed: September 13, 2022
    Date of Patent: December 26, 2023
    Assignee: Hitachi, Ltd.
    Inventors: Yoshihiro Yoshii, Masahiro Tsuruya, Ryosuke Tatsumi
  • Publication number: 20230315323
    Abstract: A first node receives a read request, determines a storage drive location where data corresponding to one or more logical addresses designated in the read request is stored, and requests transfer of the data at the one or more logical addresses, from the second node, when the storage drive location is the second node. The second node reads a data chunk containing the data designated by the one or more logical addresses, from one or more storage drives, determines whether to decompress the data chunk based on the size of the data chunk and the size of the one or more logical addresses, decompresses the data chunk based on the determination as to decompress the data chunk, extracts data at the one or more logical addresses, and transfers the extracted data to the first node.
    Type: Application
    Filed: September 13, 2022
    Publication date: October 5, 2023
    Inventors: Yoshihiro YOSHII, Masahiro TSURUYA, Ryosuke TATSUMI
  • Patent number: 11755249
    Abstract: To improve performance of a storage system. The storage system includes a plurality of storage nodes that communicate via a network. Each of the plurality of storage nodes includes one or more controllers. At least one controller in the controllers specifies at least two controllers that allocate a cache sub-area where write data is stored based on a controller that receives the write data from a host and a controller that processes the write date, and the cache sub-area is allocated in the specified controllers.
    Type: Grant
    Filed: April 28, 2022
    Date of Patent: September 12, 2023
    Assignee: HITACHI, LTD.
    Inventors: Masahiro Tsuruya, Tomohiro Yoshihara, Ryosuke Tatsumi, Shinsuke Izawa
  • Publication number: 20230205419
    Abstract: The storage device includes a first memory, a process device that stores data in the first memory and reads the data from the first memory, and an accelerator that includes a second memory different from the first memory. The accelerator stores compressed data stored in one or more storage drives storing data, in the second memory, decompresses the compressed data stored in the second memory to generate plaintext data, extracts data designated in the process device from the plaintext data, and transmits the extracted designated data to the first memory.
    Type: Application
    Filed: March 7, 2023
    Publication date: June 29, 2023
    Inventors: Masahiro TSURUYA, Nagamasa MIZUSHIMA, Tomohiro YOSHIHARA, Kentaro SHIMADA
  • Patent number: 11625168
    Abstract: The storage device includes a first memory, a process device that stores data in the first memory and reads the data from the first memory, and an accelerator that includes a second memory different from the first memory. The accelerator stores compressed data stored in one or more storage drives storing data, in the second memory, decompresses the compressed data stored in the second memory to generate plaintext data, extracts data designated in the process device from the plaintext data, and transmits the extracted designated data to the first memory.
    Type: Grant
    Filed: May 25, 2022
    Date of Patent: April 11, 2023
    Assignee: HITACHI, LTD.
    Inventors: Masahiro Tsuruya, Nagamasa Mizushima, Tomohiro Yoshihara, Kentaro Shimada
  • Patent number: 11481114
    Abstract: A storage apparatus includes: a flash memory that provides a storage area; a controller that controls writing and reading of data to and from the storage area; and a buffer memory that temporarily stores data to be written in the storage area, in which the controller selects one compression method from a first reversible compression method and a second reversible compression method based on access performance to the flash memory, and determines to compress data based on the selected one compression method and to write the compressed data to the storage area, and the first reversible compression method has a lower compression ratio and a slower compression speed than the second reversible compression method.
    Type: Grant
    Filed: November 8, 2016
    Date of Patent: October 25, 2022
    Assignee: HITACHI, LTD.
    Inventors: Nagamasa Mizushima, Masahiro Tsuruya, Masahiro Arai
  • Publication number: 20220291842
    Abstract: The storage device includes a first memory, a process device that stores data in the first memory and reads the data from the first memory, and an accelerator that includes a second memory different from the first memory. The accelerator stores compressed data stored in one or more storage drives storing data, in the second memory, decompresses the compressed data stored in the second memory to generate plaintext data, extracts data designated in the process device from the plaintext data, and transmits the extracted designated data to the first memory.
    Type: Application
    Filed: May 25, 2022
    Publication date: September 15, 2022
    Inventors: Masahiro TSURUYA, Nagamasa MIZUSHIMA, Tomohiro YOSHIHARA, Kentaro SHIMADA
  • Publication number: 20220253250
    Abstract: To improve performance of a storage system. The storage system includes a plurality of storage nodes that communicate via a network. Each of the plurality of storage nodes includes one or more controllers. At least one controller in the controllers specifies at least two controllers that allocate a cache sub-area where write data is stored based on a controller that receives the write data from a host and a controller that processes the write date, and the cache sub-area is allocated in the specified controllers.
    Type: Application
    Filed: April 28, 2022
    Publication date: August 11, 2022
    Inventors: Masahiro TSURUYA, Tomohiro YOSHIHARA, Ryosuke TATSUMI, Shinsuke IZAWA
  • Patent number: 11360669
    Abstract: The storage device includes a first memory, a process device that stores data in the first memory and reads the data from the first memory, and an accelerator that includes a second memory different from the first memory. The accelerator stores compressed data stored in one or more storage drives storing data, in the second memory, decompresses the compressed data stored in the second memory to generate plaintext data, extracts data designated in the process device from the plaintext data, and transmits the extracted designated data to the first memory.
    Type: Grant
    Filed: February 10, 2021
    Date of Patent: June 14, 2022
    Assignee: HITACHI, LTD.
    Inventors: Masahiro Tsuruya, Nagamasa Mizushima, Tomohiro Yoshihara, Kentaro Shimada
  • Patent number: 11347432
    Abstract: To improve performance of a storage system. The storage system includes a plurality of storage nodes that communicate via a network. Each of the plurality of storage nodes includes one or more controllers. At least one controller in the controllers specifies at least two controllers that allocate a cache sub-area where write data is stored based on a controller that receives the write data from a host and a controller that processes the write date, and the cache sub-area is allocated in the specified controllers.
    Type: Grant
    Filed: August 27, 2019
    Date of Patent: May 31, 2022
    Assignee: HITACHI, LTD.
    Inventors: Masahiro Tsuruya, Tomohiro Yoshihara, Ryosuke Tatsumi, Shinsuke Izawa
  • Publication number: 20220164146
    Abstract: A storage system includes: a controller which includes a processor and a memory; and one or more storage devices. The controller sets a plurality of logical volumes, stores data related to a write request in the memory when the write request is received in the logical volume, and collectively compresses a plurality of pieces of data related to the write request in the memory and writes the compressed data to the storage device. When a plurality of pieces of data related to a plurality of the logical volumes that need to be written to the storage device exist in the memory, the controller selects the plurality of pieces of data in an identical logical volume, and collectively compresses the plurality of pieces of selected data and writes the compressed data in the storage device.
    Type: Application
    Filed: September 13, 2021
    Publication date: May 26, 2022
    Inventors: Masahiro TSURUYA, Norio SHIMOZONO, Akira YAMAMOTO, Kentaro SHIMADA, Takashi NAGAO
  • Publication number: 20210311664
    Abstract: The storage device includes a first memory, a process device that stores data in the first memory and reads the data from the first memory, and an accelerator that includes a second memory different from the first memory. The accelerator stores compressed data stored in one or more storage drives storing data, in the second memory, decompresses the compressed data stored in the second memory to generate plaintext data, extracts data designated in the process device from the plaintext data, and transmits the extracted designated data to the first memory.
    Type: Application
    Filed: February 10, 2021
    Publication date: October 7, 2021
    Inventors: Masahiro TSURUYA, Nagamasa MIZUSHIMA, Tomohiro YOSHIHARA, Kentaro SHIMADA
  • Patent number: 10908988
    Abstract: A storage apparatus includes: a controller; and a plurality of storage drives, wherein the controller issues a read command for specifying a value associated with an error correction mode to a first storage drive of the plurality of storage drives, the first storage drive selects the error correction mode associated with the value specified by the read command from a plurality of error correction modes, the plurality of error correction modes include a first error correction mode and a second error correction mode with a higher correcting capability and a longer maximum delay time than those of the first error correction mode, and the first storage drive executes a read of data from a storage medium in the selected error correction mode.
    Type: Grant
    Filed: April 3, 2017
    Date of Patent: February 2, 2021
    Assignee: Hitachi, Ltd.
    Inventors: Mitsuo Date, Hideyuki Koseki, Akifumi Suzuki, Masahiro Tsuruya
  • Patent number: 10896700
    Abstract: A system including a first storage drive and a superior device superior to the first storage drive, wherein the superior device specifies a first allowable environmental temperature that makes the remaining lifetime of the first storage drive longer than the remaining operation schedule period of the first storage drive, and controls an environmental temperature adjusting device that adjusts the environmental temperature of the first storage drive on the basis of the first allowable environmental temperature.
    Type: Grant
    Filed: April 19, 2017
    Date of Patent: January 19, 2021
    Assignee: HITACHI, LTD.
    Inventors: Masahiro Tsuruya, Masahiro Arai, Akifumi Suzuki, Shimpei Nomura
  • Patent number: 10884630
    Abstract: A storage system includes a controller and a nonvolatile memory drive, in which the controller transmits a write request that designates a volume identifier of a volume to be provided to a host, to the nonvolatile memory drive; the nonvolatile memory drive exclusively allocates a free block selected from a plurality of blocks to the volume identifier; write data of the write request is written to the free block; when the write data is update write data, an area that stores data to be updated is changed to an invalid data area; and after valid data of a block including the invalid data area is migrated to another block, all data of the block including the invalid data area is erased.
    Type: Grant
    Filed: April 13, 2017
    Date of Patent: January 5, 2021
    Assignee: Hitachi, Ltd.
    Inventors: Koji Hosogi, Naoya Okada, Akifumi Suzuki, Hideyuki Koseki, Masahiro Tsuruya
  • Patent number: 10768838
    Abstract: When a logical capacity of a nonvolatile semiconductor memory is increased, after a logical capacity which is allocated to a RAID group but unused is released, the RAID group is reconfigured to include the released logical capacity and the increased logical capacity. When the logical capacity of the nonvolatile semiconductor memory is reduced, after the reduced logical capacity is released from the RAID group, the RAID group is reconfigured with the released logical capacity.
    Type: Grant
    Filed: January 12, 2017
    Date of Patent: September 8, 2020
    Assignee: HITACHI, LTD.
    Inventors: Shimpei Nomura, Masahiro Tsuruya, Akifumi Suzuki
  • Publication number: 20200272359
    Abstract: To improve performance of a storage system. The storage system includes a plurality of storage nodes that communicate via a network. Each of the plurality of storage nodes includes one or more controllers. At least one controller in the controllers specifies at least two controllers that allocate a cache sub-area where write data is stored based on a controller that receives the write data from a host and a controller that processes the write date, and the cache sub-area is allocated in the specified controllers.
    Type: Application
    Filed: August 27, 2019
    Publication date: August 27, 2020
    Inventors: Masahiro TSURUYA, Tomohiro YOSHIHARA, Ryosuke TATSUMI, Shinsuke IZAWA
  • Publication number: 20200073586
    Abstract: An information processing apparatus includes a storage controller and a storage device. The storage controller manages a first address space in which data is recorded in a log-structured format in response to a write request from a host. The storage device manages a second address space in which data is recorded in a log-structured format in response to a write request from the storage controller. The storage controller sets a unit by which the storage controller performs garbage collection in the first address space to a multiple of a unit by which the storage device performs garbage collection in the second address space.
    Type: Application
    Filed: March 5, 2019
    Publication date: March 5, 2020
    Inventors: Naruki KURATA, Hiroki FUJII, Masahiro TSURUYA
  • Publication number: 20190361611
    Abstract: A storage system includes a controller and a nonvolatile memory drive, in which the controller transmits a write request that designates a volume identifier of a volume to be provided to a host, to the nonvolatile memory drive; the nonvolatile memory drive exclusively allocates a free block selected from a plurality of blocks to the volume identifier; write data of the write request is written to the free block; when the write data is update write data, an area that stores data to be updated is changed to an invalid data area; and after valid data of a block including the invalid data area is migrated to another block, all data of the block including the invalid data area is erased.
    Type: Application
    Filed: April 13, 2017
    Publication date: November 28, 2019
    Inventors: Koji HOSOGI, Naoya OKADA, Akifumi SUZUKI, Hideyuki KOSEKI, Masahiro TSURUYA