Abstract: In the manufacture of a semiconductor device having a high-performance and high-reliability, a silicon nitride film 17 for self alignment, which film is formed to cover the gate electrode of a MISFET, is formed at a substrate temperature of 400° C. or greater by plasma CVD using a raw material gas including monosilane and nitrogen. A silicon nitride film 44 constituting a passivation film is formed at a substrate temperature of about 350° C. by plasma CVD using a raw material gas including monosilane, ammonia and nitrogen. The hydrogen content contained in the silicon nitride film 17 is smaller than that contained in the silicon nitride film 44, making it possible to suppress hydrogen release from the silicon nitride film 17.

Abstract: In the manufacture of a semiconductor device having a high-performance and high-reliability, a silicon nitride film 17 for self alignment, which film is formed to cover the gate electrode of a MISFET, is formed at a substrate temperature of 400° C. or greater by plasma CVD using a raw material gas including monosilane and nitrogen. A silicon nitride film 44 constituting a passivation film is formed at a substrate temperature of about 350° C. by plasma CVD using a raw material gas including monosilane, ammonia and nitrogen. The hydrogen content contained in the silicon nitride film 17 is smaller than that contained in the silicon nitride film 44, making it possible to suppress hydrogen release from the silicon nitride film 17.

Abstract: In the manufacture of a semiconductor device having a high-performance and high-reliability, a silicon nitride film 17 for self alignment, which film is formed to cover the gate electrode of a MISFET, is formed at a substrate temperature of 400° C. or greater by plasma CVD using a raw material gas including monosilane and nitrogen. A silicon nitride film 44 constituting a passivation film is formed at a substrate temperature of about 350° C. by plasma CVD using a raw material gas including monosilane, ammonia and nitrogen. The hydrogen content contained in the silicon nitride film 17 is smaller than that contained in the silicon nitride film 44, making it possible to suppress hydrogen release from the silicon nitride film 17.

Abstract: The present invention provides a MOS semiconductor device which enables gate leakage current reduction with a thinner gate dielectric film for higher speed, and a production method thereof. According to the present invention, a gate dielectric film 6 is made as follows: after forming a silicon nitride film 3 with a specified thickness, it is annealed in an oxidizing atmosphere to form silicon oxide 4 on the silicon nitride film 3, then this silicon oxide 4 is completely removed by exposure to a dissolving liquid. As a result, at depths between 0.12 nm and 0.5 nm from the top surface of the silicon nitride film 3 in the gate dielectric film 6 whose main constituent elements are silicon, nitrogen and oxygen, the nitrogen concentration is higher than the oxygen concentration. This enables the use of a thinner gate dielectric film with silicon, nitrogen and oxygen as main constituent elements while at the same time realizing reduction in leakage currents.

Abstract: In the manufacture of a semiconductor device having a high-performance and high-reliability, a silicon nitride film 17 for self alignment, which film is formed to cover the gate electrode of a MISFET, is formed at a substrate temperature of 400° C. or greater by plasma CVD using a raw material gas including monosilane and nitrogen. A silicon nitride film 44 constituting a passivation film is formed at a substrate temperature of about 350° C. by plasma CVD using a raw material gas including monosilane, ammonia and nitrogen. The hydrogen content contained in the silicon nitride film 17 is smaller than that contained in the silicon nitride film 44, making it possible to suppress hydrogen release from the silicon nitride film 17.

Abstract: The influence of ion milling is extremely suppressed even in a composite magnetic thin film head comprising a magnetoresistive thin film head used by passing an electric current perpendicularly to a multilayer structure. The number of ion milling steps after the formation of a magnetoresistive thin film head is reduced as much as possible, whereby the influence of electrostatic charging arising from an ion milling apparatus is obviated. In specific embodiments, an inductive magnetic thin film head is first formed on a substrate, and thereafter a magnetoresistive thin film head is formed thereon. The magneto resistive thin film head includes a magneto resistive film having a multilayer structure and configured to be used by passing a detection current perpendicularly to the multilayer structure. In one embodiment, the inductive magnetic thin film head has a structure in which a coil is buried at the same horizontal position as a lower pole.

Abstract: The present invention provides a MOS semiconductor device which enables gate leakage current reduction with a thinner gate dielectric film for higher speed, and a production method thereof. According to the present invention, a gate dielectric film 6 is made as follows: after forming a silicon nitride film 3 with a specified thickness, it is annealed in an oxidizing atmosphere to form silicon oxide 4 on the silicon nitride film 3, then this silicon oxide 4 is completely removed by exposure to a dissolving liquid. As a result, at depths between 0.12 nm and 0.5 nm from the top surface of the silicon nitride film 3 in the gate dielectric film 6 whose main constituent elements are silicon, nitrogen and oxygen, the nitrogen concentration is higher than the oxygen concentration. This enables the use of a thinner gate dielectric film with silicon, nitrogen and oxygen as main constituent elements while at the same time realizing reduction in leakage currents.

Abstract: Disclosed is a semiconductor device (e.g., nonvolatile semiconductor memory device) and method of forming the device. The device includes a gate electrode (e.g., floating gate electrode) having a first layer of an amorphous silicon film, or a polycrystalline silicon thin film or a film of a combination of amorphous and polycrystalline silicon, on the gate insulating film. Where the film includes polycrystalline silicon, the thickness of the film is less than 10 nm. A thicker polycrystalline silicon film can be provided on or overlying the first layer. The memory device can increase the write/erase current significantly without increasing the low electric field leakage current after application of stresses, which in turn reduces write/erase time substantially.

Abstract: The present invention provides a MOS semiconductor device which enables gate leakage current reduction with a thinner gate dielectric film for higher speed, and a production method thereof. According to the present invention, a gate dielectric film 6 is made as follows: after forming a silicon nitride film 3 with a specified thickness, it is annealed in an oxidizing atmosphere to form silicon oxide 4 on the silicon nitride film 3, then this silicon oxide 4 is completely removed by exposure to a dissolving liquid. As a result, at depths between 0.12 nm and 0.5 nm from the top surface of the silicon nitride film 3 in the gate dielectric film 6 whose main constituent elements are silicon, nitrogen and oxygen, the nitrogen concentration is higher than the oxygen concentration. This enables the use of a thinner gate dielectric film with silicon, nitrogen and oxygen as main constituent elements while at the same time realizing reduction in leakage currents.

Abstract: Disclosed is a semiconductor device (e.g., nonvolatile semiconductor memory device) and method of forming the device. The device includes a gate electrode (e.g., floating gate electrode) having a first layer of an amorphous silicon film, or a polycrystalline silicon thin film or a film of a combination of amorphous and polycrystalline silicon, on the gate insulating film. Where the film includes polycrystalline silicon, the thickness of the film is less than 10 nm. A thicker polycrystalline silicon film can be provided on or overlying the first layer. The memory device can increase the write/erase current significantly without increasing the low electric field leakage current after application of stresses, which in turn reduces write/erase time substantially.

Abstract: Disclosed is a semiconductor device (e.g., nonvolatile semiconductor memory device) and method of forming the device. The device includes a gate electrode (e.g., floating gate electrode) having a first layer of an amorphous silicon film, or a polycrystalline silicon thin film or a film of a combination of amorphous and polycrystalline silicon, on the gate insulating film. Where the film includes polycrystalline silicon, the thickness of the film is less than 10 nm. A thicker polycrystalline silicon film can be provided on or overlying the first layer. The memory device can increase the write/erase current significantly without increasing the low electric field leakage current after application of stresses, which in turn reduces write/erase time substantially.

Abstract: Provided is an improved fabrication process for a semiconductor device by means of which in fabrication of insulated gate semiconductor devices having gate insulating films including silicon oxide films of different thickness, no contamination from a photoresist is ensured in a silicon oxide film, generation of defects in the silicon oxide film to be otherwise caused by aqueous solution treatments is suppressed, and thereby variability of characteristics among the semiconductor devices is suppressed.

Abstract: The present invention provides a MOS semiconductor device which enables gate leakage current reduction with a thinner gate dielectric film for higher speed, and a production method thereof. According to the present invention, a gate dielectric film 6 is made as follows: after forming a silicon nitride film 3 with a specified thickness, it is annealed in an oxidizing atmosphere to form silicon oxide 4 on the silicon nitride film 3, then this silicon oxide 4 is completely removed by exposure to a dissolving liquid. As a result, at depths between 0.12 nm and 0.5 nm from the top surface of the silicon nitride film 3 in the gate dielectric film 6 whose main constituent elements are silicon, nitrogen and oxygen, the nitrogen concentration is higher than the oxygen concentration. This enables the use of a thinner gate dielectric film with silicon, nitrogen and oxygen as main constituent elements while at the same time realizing reduction in leakage currents.

Abstract: Provided is an improved fabrication process for a semiconductor device by means of which in fabrication of insulated gate semiconductor devices having gate insulating films including silicon oxide films of different thickness, no contamination from a photoresist is ensured in a silicon oxide film, generation of defects in the silicon oxide film to be otherwise caused by aqueous solution treatments is suppressed, and thereby variability of characteristics among the semiconductor devices is suppressed.

Abstract: Disclosed is a semiconductor device (e.g., nonvolatile semiconductor memory device) and method of forming the device. The device includes a gate electrode (e.g., floating gate electrode) having a first layer of an amorphous silicon film, or a polycrystalline silicon thin film or a film of a combination of amorphous and polycrystalline silicon, on the gate insulating film. Where the film includes polycrystalline silicon, the thickness of the film is less than 10 nm. A thicker polycrystalline silicon film can be provided on or overlying the first layer. The memory device can increase the write/erase current significantly without increasing the low electric field leakage current after application of stresses, which in turn reduces write/erase time substantially.

Abstract: Before a high permittivity interlayer insulating film of a non-volatile memory having a two-level gate electrode structure, a surface of a substrate in a peripheral circuit MOS area is successively covered with a thermal oxide film and a polycrystalline silicon film. Before the interlayer insulating film is selectively removed on the peripheral circuit MOS area, the surface of the interlayer insulating film of the non-volatile memory is covered with a polycrystalline silicon film. When the interlayer insulating film in the peripheral circuit MOS area is removed, the polycrystalline silicon film as a lower layer in the peripheral circuit area serves as a buffer layer against contamination or damage due to the etching, and the conductive layer on the surface of the interlayer insulating film in the non-volatile memory portion also serves as a buffer layer against the contamination or damage due to the etching.