Patents by Inventor Masahiro Yoneda
Masahiro Yoneda has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240139719Abstract: A catalyst for methane synthesis is made up from layered double hydroxides represented by the following general formula (1). [M2+1-xM3+x(OH)2]x+[An?x/n·yH2O]??(1) In formula (1), M2+ is Ni2+ and M3+ is Al3+ or Cr3+. Further, An? is CO32?. Furthermore, the term x lies within a range of 0.19 to 0.34 (0.19?x?0.34), and y is 0 or a positive integer.Type: ApplicationFiled: October 23, 2023Publication date: May 2, 2024Inventors: Hideaki YONEDA, Kazuki YANAGISAWA, Misato MAKI, Masahiro MOHRI, Jumpei YOSHIDA, Noritatsu TSUBAKI
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Publication number: 20240141525Abstract: An electrosynthesis system is equipped with an electrolysis device that carries out electrolysis on carbon dioxide gas and water vapor, a synthesizing device that synthesizes a hydrocarbon gas from hydrogen gas and carbon monoxide gas that are generated by the electrolysis, and a control device. The control device adjusts a flow rate of the water vapor supplied to the electrolysis device, in a manner so that a first concentration ratio, which is a concentration ratio between the hydrogen gas and the carbon monoxide gas in a mixed gas discharged from the electrolysis device and containing the hydrogen gas and the carbon monoxide gas, becomes a predetermined target concentration ratio.Type: ApplicationFiled: October 26, 2023Publication date: May 2, 2024Inventors: Masahiro MOHRI, Kazuki YANAGISAWA, Misato MAKI, Hideaki YONEDA, Jumpei YOSHIDA
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Patent number: 9320264Abstract: A nest box (1) for bumblebees that provides sufficient ventilation inside the nest box (1). The provided nest box (1) with a bumblebees hive (2) inside resolves the problems of insufficient ventilation, by being mounted with a ventilation panel (14), comprising ventilation holes (13) in size(s) that enable ventilation but at the same time bumblebees from passing through.Type: GrantFiled: January 24, 2011Date of Patent: April 26, 2016Assignees: Biobest Belgium NV, Tokai Trading Co. Ltd.Inventors: Willem Steven Paul Keppens, Tim Bollens, Felix Leopold Wackers, Hidetoshi Yokoi, Masahiro Yoneda, Takayuki Aoki
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Publication number: 20120295514Abstract: This invention relates to a nest box (1) for bumblebees that provides sufficient ventilation inside the nest box (1). The provided nest box (1) with a bumblebees hive (2) inside resolves the problems of insufficient ventilation, by being mounted with a ventilation panel (14), comprising ventilation holes (13) in size(s) that enable ventilation but at the same time bumblebees from passing through.Type: ApplicationFiled: January 24, 2011Publication date: November 22, 2012Applicants: TOKAI TRADING CO., LTD., BIOBEST BELGIUM NVInventors: Willem Steven Paul Keppens, Tim Bollens, Felix Leopold Wackers, Hidetoshi Yokoi, Masahiro Yoneda, Takayuki Aoki
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Patent number: 5784739Abstract: As a countermeasure against storms for long span, particularly super-long span suspension bridges with the center span exceeding 2,000 m, there is provided a super-long span suspension bridge which can be improved of its static and dynamic wind resistance performance by applying a mass to a portion of the girder. In a suspension bridge with the center span exceeding 2,000 m, a mass application member capable of temporarily carrying a predetermined amount of additional load is provided on either side of the stiffening girder for a distance equal to 1/3 at the maximum of the center span so that a mass weighing 30% or less of the weight of the girder is temporarily applied in the mass application member in the girder on the windward side when the bridge is subjected to a storm, and cross stays are provided each at a point inward from either end of the center span section at a distance equal to 1/4 to 1/3 of the center span.Type: GrantFiled: October 2, 1996Date of Patent: July 28, 1998Assignee: Kawada Industries, Inc.Inventors: Tadaki Kawada, Masahiro Yoneda, Shunzo Nakazaki
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Patent number: 5536926Abstract: An optical scanner and an optical scanning device, an optical sensor unit, a coded data reader, and a POS system employing an optical scanner. The optical comprises an elastically deformable element, a vibrational input segment disposed at a first end of the elastically deformable element, a driven segment disposed at a second end of the elastically deformable element, a vibration source for inducing vibration in the vibrational input segment, whereby the vibration induced in the vibrational input segment produces elastic deformation of the elastically deformable element and consequent movement of the driven segment, and a stop for limiting a range of the movement of the driven segment.Type: GrantFiled: December 22, 1994Date of Patent: July 16, 1996Assignee: Omron CorporationInventors: Masaaki Ikeda, Hiroshi Goto, Kenji Takemura, Hidenobu Umeda, Masahiro Yoneda, Atsushi Irie, Kiyotoshi Ookura, Norimasa Yamanaka, Hiromi Totani
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Patent number: 5366834Abstract: In a cathode-ray tube phosphor, a layer consisting of a substantially uniform SiO.sub.2 film or an organic film consisting essentially of at least one type of a polymer selected from the group consisting of an acrylic resin, gelatin, alginic acid, chitosan, and a urea resin is formed as a first layer on the surface of a phosphor particle, and a layer containing at least one type of a metal selected from the group consisting of Zn, Al, and an alkali earth metal and at least one member selected from the group consisting of a colloidal silica, an alumina sol, and a titania sol each having a particle size of 50 nm or less is formed as a second layer on the first layer. This phosphor is excellent in oxidation resistance and dispersibility.Type: GrantFiled: May 5, 1993Date of Patent: November 22, 1994Assignee: Nichia Kagaku Kogyo K.K.Inventors: Masahiro Yoneda, Shoichi Bando, Ichiro Takeoka
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Patent number: 5292401Abstract: A fine pattern forming apparatus includes a stage and an opposed electrode at least one of which is made of a magnetic material. A magnetic field is applied to this stage or opposed electrode to provide a predetermined gap between the stage and the opposed electrode for a fine pattern formation. In consequence, optimum etching conditions (including etching uniformity, etch rate and etching direction) can be assured without generating dust. As a result, damage caused by the plasma can be reduced, and the etch rate can be increased.Type: GrantFiled: April 8, 1993Date of Patent: March 8, 1994Assignee: Mitsubishi Denki Kabushiki KaishaInventor: Masahiro Yoneda
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Patent number: 5285092Abstract: A capacitor of a semiconductor memory device includes a planar type capacitor portion formed on a surface of an impurity region and a stacked type capacitor portion extending above the gate electrode. The stacked capacitor portion has a three-layer structure of polycrystalline silicon in which upper, lower and side surfaces of a lower electrode are surrounded by a dielectric layer and the upper electrode. A portion of a dielectric layer in the stacked capacitor portion is coupled to another dielectric layer formed on the surface of one impurity region. The capacitor has a planar type capacitor provided in the planar area of occupation of the stacked capacitor portion, whereby the capacitance of the capacitor can be increased without increasing the planar area of occupation.Type: GrantFiled: July 24, 1992Date of Patent: February 8, 1994Assignee: Mitsubishi Denki Kabushiki KaishaInventor: Masahiro Yoneda
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Patent number: 5277740Abstract: A fine pattern forming apparatus includes an elastic wave generating device which is provided on the wall of a vacuum chamber. A fine pattern forming method involves formation of a fine pattern while an elastic wave is being applied to the vacuum chamber by the elastic wave generating device. Since the fine pattern is formed while the elastic wave is applied to the vacuum chamber the, uniformity of the plasma density and of the electron density is improved and attachment of reaction products to the vacuum chamber is prevented.Type: GrantFiled: May 20, 1992Date of Patent: January 11, 1994Assignee: Mitsubishi Denki Kabushiki KaishaInventor: Masahiro Yoneda
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Patent number: 5258266Abstract: A method of forming a minute pattern with controlled resist profile by using chemically amplifying type resist and deep UV ray is disclosed. A positive chemically amplifying type resist is applied on a silicon substrate, to form a resist film of the resist on the silicon substrate. The resist film is selectively irradiated with KrF excimer laser beam by using a photomask. Thereafter, an electric field directed vertically downward is applied to the resist film while the resist film is heated. According to this method, H.sup.+ ions which are catalyst for destroying the dissolution inhibiting capability of the dissolution inhibitor generated in the resist film move vertically downward, so that diffusion of the H.sup.+ ions in the lateral direction during heating can be prevented. Consequently, a positive minute pattern having sidewall formed vertical to the substrate can be provided.Type: GrantFiled: August 6, 1992Date of Patent: November 2, 1993Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Akira Tokui, Masahiro Yoneda
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Patent number: 5228940Abstract: A fine pattern forming apparatus includes a stage and an opposed electrode at least one of which is made of a magnetic material. A magnetic field is applied to this stage or opposed electrode to provide a predetermined gap between the stage and the opposed electrode for a fine pattern formation. In consequence, optimum etching conditions (including etching uniformity, etch rate and etching direction) can be assured without generating dust. As a result, damage caused by the plasma can be reduced, and the etch rate can be increased.Type: GrantFiled: April 10, 1992Date of Patent: July 20, 1993Assignee: Mitsubishi Denki Kabushiki KaishaInventor: Masahiro Yoneda
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Patent number: 5219781Abstract: A capacitor of a semiconductor memory device includes a planar type capacitor portion formed on a surface of an impurity region and a stacked type capacitor portion extending above the gate electrode. The stacked capacitor portion has a three-layer structure of polycrystalline silicon in which upper, lower and side surfaces of a lower electrode are surrounded by a dielectric layer and the upper electrode. A portion of a dielectric layer in the stacked capacitor portion is coupled to another dielectric layer formed on the surface of one impurity region. The capacitor has a planar type capacitor provided in the planar area of occupation of the stacked capacitor portion, whereby the capacitance of the capacitor can be increased without increasing the planar area of occupation.Type: GrantFiled: October 13, 1992Date of Patent: June 15, 1993Assignee: Mitsubishi Denki Kabushiki KaishaInventor: Masahiro Yoneda
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Patent number: 5177574Abstract: A capacitor of a semiconductor memory device includes a planar type capacitor portion formed on a surface of an impurity region and a stacked type capacitor portion extending above the gate electrode. The stacked capacitor portion has a three-layer structure of polycrystalline silicon in which upper, lower and side surfaces of a lower electrode are surrounded by a dielectric layer and the upper electrode. A portion of a dielectric layer in the stacked capacitor portion is coupled to another dielectric layer formed on the surface of one impurity region. The capacitor has a planar type capacitor provided in the planar area of occupation of the stacked capacitor portion, whereby the capacitance of the capacitor can be increased without increasing the planar area of occupation.Type: GrantFiled: December 6, 1989Date of Patent: January 5, 1993Assignee: Mitsubishi Denki Kabushiki KaishaInventor: Masahiro Yoneda
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Patent number: 5175118Abstract: A MOS FET comprises a gate electrode and source and drain regions. Conductive layers for electrode are formed on surfaces of the source and drain regions. The conductive layers for electrode are formed by a multilayer structure including a high melting point metal silicide film in contact with the source and drain regions and a polycrystaline silicon layer formed thereon. The gate electrode is formed of polysilicon. The gate electrode has a structure in which part of the gate electrode extends over the conductive layers for electrode formed on the source and drain regions. Such structure reduces the resistance of the interconnection layers for electrodes and realizes reduction in width of the gate electrode. In the manufacturing method, the patterning of the conductive layers for electrodes on the surface of the source/drain regions comprises the steps of etching the polycrystalline silicon layer by dry etching, and ethcing the high melting point metal silicide layer by wet etching.Type: GrantFiled: November 5, 1991Date of Patent: December 29, 1992Assignee: Mitsubishi Denki Kabushiki KaishaInventor: Masahiro Yoneda
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Patent number: 5158861Abstract: A method of forming a minute pattern with controlled resist profile uses a chemically amplifying type resist and deep UV rays. Microposit SAL601-ER7 is applied on a silicon substrate, to form a resist film of the resist on the silicon substrate. The resist film is selectively irradiated with KrF excimer laser beam by using a photomask. Thereafter, an electric field directed vertically downward is applied to the resist film while the resist film is heated. According to this method, H.sup.+ ions which are a catalyst for cross linking generated in the resist film move vertically downward, so that diffusion of the H.sup.+ ions in the lateral direction during heating can be prevented. Consequently, negative minute patterns having sidewalls formed vertical to the substrate can be provided.Type: GrantFiled: March 30, 1990Date of Patent: October 27, 1992Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Akira Tokui, Masahiro Yoneda
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Patent number: 5079617Abstract: A MOS FET comprises a gate electrode and source and drain regions. Conductive layers for electrode are formed on surfaces of the source and drain regions. The conductive layers for electrode are formed by a multilayer structure including a high melting point metal silicide film in contact with the source and drain regions and a polycrystalline silicon layer formed thereon. The gate electrode is formed of polysilicon. The gate electrode has a structure in which part of the gate electrode extends over the conductive layers for electrode formed on the source and drain regions. Such structure reduces the resistance of the interconnection layers for electrodes and realizes reduction in width of the gate electrode. In the manufacturing method, the patterning of the conductive layers for electrodes on the surface of the source/drain regions comprises the steps of etching the polycrystalline silicon layer by dry etching, and etching the high melting point metal silicide layer by wet etching.Type: GrantFiled: September 11, 1989Date of Patent: January 7, 1992Assignee: Mitsubishi Denki Kabushiki KaishaInventor: Masahiro Yoneda
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Patent number: 5041334Abstract: A pigment-attached phosphor in which pigment particles are attached to the surfaces of phosphor particles by a binder, the binder being 0.01 to 1.0 parts by weight and preferably 0.05 to 0.80 parts by weight of gelatin and 0.01 to 0.5 parts by weight and preferably 0.02 to 0.40 parts by weight of urea resin, all against 100 parts by weight of phosphor, the weight ratio of the gelatin and urea resin being within a range of 1:1 to 10:1 and preferably 1:1 to 8:1. The gelatin and urea resin ensure a strong and better attachment of the pigment particles to the surfaces of the phosphor particles.Type: GrantFiled: December 19, 1989Date of Patent: August 20, 1991Assignee: Nichia Kagaku Kogyo K.K.Inventors: Shoji Nakajima, Masahiro Yoneda
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Patent number: 4984199Abstract: A dynamic type semiconductor device comprises a memory cell array including a plurality of cell groups, each of the cell groups including four adjacent memory cells disposed in a point symmetry fashion, with a single contact hole formed at the center of the point symmetry to be common to the four memory cells, in which the four memory cells and bit lines are connected through the single contact hole.Type: GrantFiled: May 30, 1989Date of Patent: January 8, 1991Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Masahiro Yoneda, Masahiro Hatanaka, Yoshio Kohno, Shinichi Satoh, Hidekazu Oda, Koichi Moriizumi
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Patent number: 4956692Abstract: Two trenches are formed at a predetermined distance on a main surface of a semiconductor substrate. An oxide film and a nitride film are successively formed on the main surface of the semiconductor including the inner surfaces of the trenches. After a resist is formed over the whole surface including the inner surfaces of the trenches, the resist is patterned to expose a portion of the nitride film on a side surface of each trench. The exposed portions of the nitride film are removed by using the patterned resist as a mask and thermal oxidation is applied. Then, an isolation oxide film is formed on a region between the trenches and an end of a bird's beak is located on a side surface of each trench and is connected to the oxide film formed in each trench.Type: GrantFiled: November 3, 1988Date of Patent: September 11, 1990Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Hiroji Ozaki, Masahiro Yoneda, Ikuo Ogoh, Yoshinori Okumura, Wataru Wakamiya, Masao Nagatomo