Patents by Inventor Masahiro Yumoto

Masahiro Yumoto has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240112081
    Abstract: In order to attain an object of generating a prediction model which not only is capable of reducing a calculation load in a prediction phase but also has a good interpretability, a prediction model generation apparatus includes: a contribution degree calculation section that calculates, with use of a test data set different from a training data set used in training of a prediction model to be tested, a degree of contribution of each of a plurality of features to a prediction result, a value of the each of the plurality of features being inputted to the prediction model to be tested; a feature selection section that selects, on the basis of the degree of contribution of the each of the plurality of features, at least one feature from among the plurality of features; and a prediction model generation section that generates a new prediction model which, upon receiving input of a value of the at least one feature selected, outputs a prediction result.
    Type: Application
    Filed: May 25, 2023
    Publication date: April 4, 2024
    Applicant: NEC Corporation
    Inventors: Eiji Yumoto, Masahiro Hayashitani, Kosuke Nishihara
  • Patent number: 7435680
    Abstract: A method of manufacturing a circuit substrate of the present invention, includes the steps of forming an n-layered (n is an integer of 1 or more) wiring layer connected electrically to a metal plate on the metal plate, forming an electroplating layer on a connection pad portion of an uppermost wiring layer of the n-layered wiring layer by an electroplating utilizing the metal plate and the wiring layer as a plating power-supply path, and removing the metal plate.
    Type: Grant
    Filed: November 30, 2005
    Date of Patent: October 14, 2008
    Assignee: Shinko Electric Industries Co., Ltd.
    Inventors: Junichi Nakamura, Tetsuo Sakaguchi, Kazuya Mukoyama, Sachiko Oda, Masahiro Yumoto
  • Publication number: 20060121719
    Abstract: A method of manufacturing a circuit substrate of the present invention, includes the steps of forming an n-layered (n is an integer of 1 or more) wiring layer connected electrically to a metal plate on the metal plate, forming an electroplating layer on a connection pad portion of an uppermost wiring layer of the n-layered wiring layer by an electroplating utilizing the metal plate and the wiring layer as a plating power-supply path, and removing the metal plate.
    Type: Application
    Filed: November 30, 2005
    Publication date: June 8, 2006
    Applicant: SHINKO ELECTRIC INDUSTRIES CO., LTD.
    Inventors: Junichi Nakamura, Tetsuo Sakaguchi, Kazuya Mukoyama, Sachiko Oda, Masahiro Yumoto
  • Patent number: 6008822
    Abstract: A graphic processing system for accomplishing high-speed processing of data conversion processing by effectively utilizing file information of input graphic data to improve processing efficiency of data processing inside blocks, and by optimizing block division.
    Type: Grant
    Filed: May 21, 1999
    Date of Patent: December 28, 1999
    Assignees: Shinko Electric Industries, Co., Ltd., Futjitsu Limited, Japan NUS Co., Ltd.
    Inventors: Masahiro Yumoto, Kiyotaka Mochizuki, Satoshi Akutagawa, Yasufumi Ishihara
  • Patent number: 5936642
    Abstract: A graphic processing system for accomplishing high-speed processing of data conversion processing by effectively utilizing file information of input graphic data to improve processing efficiency of data processing inside blocks, and by optimizing block division.
    Type: Grant
    Filed: March 27, 1997
    Date of Patent: August 10, 1999
    Assignees: Shinko Electric Industries, Co., Ltd., Fujitsu Limited, Japan NUS Co., Ltd.
    Inventors: Masahiro Yumoto, Kiyotaka Mochizuki, Satoshi Akutagawa, Yasufumi Ishihara
  • Patent number: 5634107
    Abstract: A plurality of data processing units each having a first controller for computing design data assigned in advance so as to generate graphic data and a first storage device for receiving transfer of the design data and storing the design data temporarily, and a second controller, for when a data storage allowable value of the first storage device which has received transfer of the design data is exceeded, recognizing a data excess flag rising on that occasion, and transferring excessive data in the design data assigned to the one data processing unit to another data processing unit, thereby controlling computation share among data processing units. The design data are converted in parallel into graphic data while monitoring is performed of the data processing units.
    Type: Grant
    Filed: October 6, 1995
    Date of Patent: May 27, 1997
    Assignee: Fujitsu Limited
    Inventors: Masahiro Yumoto, Kenichi Kobayashi
  • Patent number: 5448494
    Abstract: An apparatus for mask data processing in which a design data format of computer aided design for an integrated circuit is transformed into mask data of an actual integrated circuit. The apparatus includes a data transformation unit for transforming a design data format of computer aided design for an integrated circuit into mask data of an actual integrated circuit, and a picture image display unit for monitoring the transformation of the design data format into the mask data. The data transformation unit includes a control central processor unit for controlling the mask data transformation, and a picture processing processor having a calculation central processor unit for a unit field.
    Type: Grant
    Filed: January 12, 1994
    Date of Patent: September 5, 1995
    Assignees: Fujitsu Limited, Japan Control Systems, Inc.
    Inventors: Kenichi Kobayashi, Masahiro Yumoto, Nobuyasu Horiuchi, Akihiro Okazaki, Hiroshi Fuji, Hiroaki Tsuda