Patents by Inventor Masahisa Iida
Masahisa Iida has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230208407Abstract: A semiconductor integrated circuit device includes: first and second transistors provided between a first power source and an output terminal; a step-down circuit that generates a second power source from the first power source; a power source switch circuit that outputs, as a fourth power source, a higher one of potentials of the second power source and a third power source; and a level shifter circuit that transits between the first power source and a fourth power source. The first transistor has a gate connected to an output of the level shifter circuit; the second transistor has a gate connected to the fourth power source.Type: ApplicationFiled: March 2, 2023Publication date: June 29, 2023Inventors: Masahisa IIDA, Masahiro GION
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Patent number: 11621705Abstract: A semiconductor integrated circuit device includes: first and second transistors provided between a first power source and an output terminal; a step-down circuit that generates a second power source from the first power source; a power source switch circuit that outputs, as a fourth power source, a higher one of potentials of the second power source and a third power source; and a level shifter circuit that transits between the first power source and a fourth power source. The first transistor has a gate connected to an output of the level shifter circuit; the second transistor has a gate connected to the fourth power source.Type: GrantFiled: December 15, 2020Date of Patent: April 4, 2023Assignee: SOCIONEXT INC.Inventors: Masahisa Iida, Masahiro Gion
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Publication number: 20220367442Abstract: In a semiconductor integrated circuit device, first and second IO cell rows are placed in an IO region on a chip. IO cells in the first IO cell row are larger in plane area than IO cells in the second IO cell row. Pads connected to the IO cells in the first IO cell row are located closer to an outer edge of the chip than any pads connected to the IO cells in the second IO cell row.Type: ApplicationFiled: July 29, 2022Publication date: November 17, 2022Inventors: Taro FUKUNAGA, Masahisa IIDA, Toshihiro NAKAMURA
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Publication number: 20220254811Abstract: An IO cell includes a first output transistor and a second output transistor. A capacitance transistor is provided between external connection pads. The capacitance transistor is placed between the output transistors and an edge of the semiconductor integrated circuit device as viewed in plan. The gate length of the capacitance transistor is smaller than the gate length of the output transistors.Type: ApplicationFiled: April 27, 2022Publication date: August 11, 2022Inventors: Masahisa IIDA, Toshihiro NAKAMURA
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Publication number: 20210105009Abstract: A semiconductor integrated circuit device includes: first and second transistors provided between a first power source and an output terminal; a step-down circuit that generates a second power source from the first power source; a power source switch circuit that outputs, as a fourth power source, a higher one of potentials of the second power source and a third power source; and a level shifter circuit that transits between the first power source and a fourth power source. The first transistor has a gate connected to an output of the level shifter circuit; the second transistor has a gate connected to the fourth power source.Type: ApplicationFiled: December 15, 2020Publication date: April 8, 2021Inventors: Masahisa IIDA, Masahiro GION
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Patent number: 10763849Abstract: A semiconductor integrated circuit includes: a power supply terminal that receives a power supply voltage; an external terminal; an output PMOS transistor connected between the power supply terminal and the external terminal; an auxiliary PMOS transistor connected between a gate of the output PMOS transistor and the external terminal; and a bias voltage generating circuit connected to a gate of the auxiliary PMOS transistor. The bias voltage generating circuit supplies a voltage lower than the power supply voltage to the gate of the auxiliary PMOS transistor, if it is necessary to maintain an OFF state of the output PMOS transistor by supplying an external voltage received at the external terminal to the gate of the output PMOS transistor.Type: GrantFiled: August 30, 2019Date of Patent: September 1, 2020Assignee: SOCIONEXT INC.Inventor: Masahisa Iida
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Patent number: 10644691Abstract: In order to provide a power supply switch circuit using only low-breakdown voltage transistors and eliminate the need for a special through-current preventing circuit, the switch control circuits output a signal ranging from a ground voltage level to a second power supply voltage level when a first power supply voltage (0 V/3.3 V) is in off-state and a second power supply voltage (0 V/1.8 V) is in on-state, and a signal ranging from the second power supply voltage level to a first power supply voltage level when the first and second power supply voltages are in on-state, thereby allowing a PMOS transistor and an NMOS transistor to turn on or off.Type: GrantFiled: October 19, 2018Date of Patent: May 5, 2020Assignee: SOCIONEXT INC.Inventor: Masahisa Iida
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Publication number: 20190386653Abstract: A semiconductor integrated circuit includes: a power supply terminal that receives a power supply voltage; an external terminal; an output PMOS transistor connected between the power supply terminal and the external terminal; an auxiliary PMOS transistor connected between a gate of the output PMOS transistor and the external terminal; and a bias voltage generating circuit connected to a gate of the auxiliary PMOS transistor. The bias voltage generating circuit supplies a voltage lower than the power supply voltage to the gate of the auxiliary PMOS transistor, if it is necessary to maintain an OFF state of the output PMOS transistor by supplying an external voltage received at the external terminal to the gate of the output PMOS transistor.Type: ApplicationFiled: August 30, 2019Publication date: December 19, 2019Inventor: Masahisa Iida
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Patent number: 10439596Abstract: In order to reduce a signal propagation delay when an input signal falls, an NMOS transistor (M1) is connected between an input terminal (1) receiving a signal having an amplitude of 3.3 V and an input of an inverter (INV1). A first PMOS transistor (M2) having a low drive capability and a second PMOS transistor (M4) having a high drive capability are connected in parallel between a power supply terminal (VDD 18) supplying 1.8 V and a gate of the NMOS transistor (M1). A gate of the first PMOS transistor (M2) is connected to the input of the inverter (INV1). A gate of the second PMOS transistor (M4) is connected to an output of the inverter (INV1).Type: GrantFiled: October 15, 2018Date of Patent: October 8, 2019Assignee: SOCIONEXT INC.Inventor: Masahisa Iida
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Patent number: 10355685Abstract: An output transistor (2) has a source connected to a VDD1 and a drain connected to an output terminal (1). A pre-driver (3) receives a signal varying in accordance with a data input signal (DIN), and provides a gate signal (SG1) to a gate of the output transistor (2), the gate signal (SG1) transiting between the VDD1 and a potential (VP) at a power source end (4). When a VDD2 is output from an output node (N1) and an assist signal (SA) makes a first transition corresponding to the transition of the gate signal (SG1) from HIGH to LOW, the drive assist circuit (20) performs an assist operation in which a potential of the output node (N1) is temporarily brought down from VDD2.Type: GrantFiled: June 6, 2018Date of Patent: July 16, 2019Assignee: SOCIONEXT INC.Inventors: Masahisa Iida, Masahiro Gion
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Publication number: 20190081616Abstract: In order to reduce a signal propagation delay when an input signal falls, an NMOS transistor (M1) is connected between an input terminal (1) receiving a signal having an amplitude of 3.3 V and an input of an inverter (INV1). A first PMOS transistor (M2) having a low drive capability and a second PMOS transistor (M4) having a high drive capability are connected in parallel between a power supply terminal (VDD 18) supplying 1.8 V and a gate of the NMOS transistor (M1). A gate of the first PMOS transistor (M2) is connected to the input of the inverter (INV1). A gate of the second PMOS transistor (M4) is connected to an output of the inverter (INV1).Type: ApplicationFiled: October 15, 2018Publication date: March 14, 2019Inventor: Masahisa IIDA
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Publication number: 20190052259Abstract: In order to provide a power supply switch circuit using only low-breakdown voltage transistors and eliminate the need for a special through-current preventing circuit, the switch control circuits output a signal ranging from a ground voltage level to a second power supply voltage level when a first power supply voltage (0 V/3.3 V) is in off-state and a second power supply voltage (0 V/1.8 V) is in on-state, and a signal ranging from the second power supply voltage level to a first power supply voltage level when the first and second power supply voltages are in on-state, thereby allowing a PMOS transistor and an NMOS transistor to turn on or off.Type: ApplicationFiled: October 19, 2018Publication date: February 14, 2019Inventor: Masahisa IIDA
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Publication number: 20180287600Abstract: An output transistor (2) has a source connected to a VDD1 and a drain connected to an output terminal (1). A pre-driver (3) receives a signal varying in accordance with a data input signal (DIN), and provides a gate signal (SG1) to a gate of the output transistor (2), the gate signal (SG1) transiting between the VDD1 and a potential (VP) at a power source end (4). When a VDD2 is output from an output node (N1) and an assist signal (SA) makes a first transition corresponding to the transition of the gate signal (SG1) from HIGH to LOW, the drive assist circuit (20) performs an assist operation in which a potential of the output node (N1) is temporarily brought down from VDD2.Type: ApplicationFiled: June 6, 2018Publication date: October 4, 2018Inventors: Masahisa IIDA, Masahiro GION
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Patent number: 8976563Abstract: In a memory device having a hierarchical bit line architecture, a main memory array is divided into two sub-memory arrays. The number of sub bit lines is twice the number of main bit lines, and global data lines are formed in the same metal interconnect layer as the main bit lines, thereby reducing an increase in the number of interconnects used in a memory macro. Furthermore, after charge sharing of the bit lines, the global data lines are kept in a pre-charge state at the time of amplification using sense amplifiers so that the global data lines function as shields of the main bit lines. This largely reduces interference noise between adjacent main bit lines to improve operating characteristics.Type: GrantFiled: May 22, 2013Date of Patent: March 10, 2015Assignee: Panasonic CorporationInventor: Masahisa Iida
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Patent number: 8791749Abstract: A power generation block configured to generate internal power by a charge pump circuit and a power supply control block configured to control the power generation block are provided. First and second power supply interconnects individually separated from an external power supply interconnect are connected to the power generation block and the power supply control block, respectively. At least any one of the power supply interconnects is provided with a filter section configured to remove noise propagating through the power supply interconnect.Type: GrantFiled: March 4, 2013Date of Patent: July 29, 2014Assignee: Panasonic CorporationInventors: Toshihiro Nakamura, Yuji Yamasaki, Masanobu Hirose, Masahisa Iida
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Patent number: 8687440Abstract: At a succeeding stage of a sense amplifier, a first data latch is provided which has the same bit number as the page length and is controlled to invariably hold the same data as that of the sense amplifier. When a column address strobe (CAS) access begins, data is transferred from the first data latch to an error checking and correcting circuit, and error correction and parity generation are performed in a pipeline process. As a result, the CAS access time and the CAS cycle time are reduced.Type: GrantFiled: April 26, 2012Date of Patent: April 1, 2014Assignee: Panasonic CorporationInventor: Masahisa Iida
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Publication number: 20130250646Abstract: In a memory device having a hierarchical bit line architecture, a main memory array is divided into two sub-memory arrays. The number of sub bit lines is twice the number of main bit lines, and global data lines are formed in the same metal interconnect layer as the main bit lines, thereby reducing an increase in the number of interconnects used in a memory macro. Furthermore, after charge sharing of the bit lines, the global data lines are kept in a pre-charge state at the time of amplification using sense amplifiers so that the global data lines function as shields of the main bit lines. This largely reduces interference noise between adjacent main bit lines to improve operating characteristics.Type: ApplicationFiled: May 22, 2013Publication date: September 26, 2013Applicant: PANASONIC CORPORATIONInventor: Masahisa IIDA
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Patent number: 8345506Abstract: In order to latch and store a word line reset level voltage (negative voltage) which is set during reset operation, a word line driver includes PMOS transistors and NMOS transistors. The word line driver further includes a stress-reducing PMOS transistor and an NMOS transistor, and also a word line bias control circuit which controls and activates a supply bias during setting of a word line, start of resetting, and a reset period.Type: GrantFiled: May 4, 2011Date of Patent: January 1, 2013Assignee: Panasonic CorporationInventor: Masahisa Iida
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Publication number: 20120213016Abstract: At a succeeding stage of a sense amplifier, a first data latch is provided which has the same bit number as the page length and is controlled to invariably hold the same data as that of the sense amplifier. When a column address strobe (CAS) access begins, data is transferred from the first data latch to an error checking and correcting circuit, and error correction and parity generation are performed in a pipeline process. As a result, the CAS access time and the CAS cycle time are reduced.Type: ApplicationFiled: April 26, 2012Publication date: August 23, 2012Applicant: PANASONIC CORPORATIONInventor: Masahisa IIDA
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Patent number: 8151173Abstract: Data latches, multiplexers, an ECC circuit section, and an input/output circuit section are arranged in columns and adjacent to each other, in an extending direction of data lines that are formed in a direction orthogonal to word lines. A layout of a data path system is formed in bit slices. Further, parity bits are equally distributed so as to cause delay times of bits to be uniform.Type: GrantFiled: August 18, 2008Date of Patent: April 3, 2012Assignee: Panasonic CorporationInventors: Masanobu Hirose, Masahisa Iida