Abstract: An input circuit comprises an input terminal for receiving an input signal, an output terminal for outputting an output signal, a node connected to the input terminal, a terminating resistor connected between the node and a ground, a potential shift element connected between the node and the output terminal, a potential source for supplying a predetermined potential, and a current source connected between the potential source and the output terminal.

Abstract: An input circuit comprises an input terminal for receiving an input signal, an output terminal for outputting an output signal, a node connected to the input terminal, a terminating resistor connected between the node and a ground, a potential shift element connected between the node and the output terminal, a potential source for supplying a predetermined potential, and a current source connected between the potential source and the output terminal.

Abstract: A chip tray includes a first member (11) having an adhesive (13) on an upper face thereof and a second member (12) having upper and lower faces and at least one chip carrying section (14) having a through hole (15) extending downwardly from a bottom of the chip carrying section to the lower face of the second member. The second member is placed upon the first member such that the upper face of the first member is opposed to the lower face of the second member.

Abstract: A chip tray comprises a first member (11) having an adhesive (13) on an upper face thereof and a second member (12) having upper and lower faces and at least one chip carrying section (14) having a through hole (15) extending downwardly from a bottom of the chip carrying section to the lower face of the second member. The second member is placed upon the first member such that the upper face of the first member is opposed to the lower face of the second member.

Abstract: There is disclosed a negative feedback amplifier provided with a feedback circuit used to make impedance variable and to improve high frequency characteristics and so configured to prevent a problem of parasitic capacity caused by a by-pass condenser. The feedback circuit connected in parallel to an inverting amplifier circuit is composed of a first feedback resistor connected in parallel to the inverting amplifier circuit, and a second feedback resistor and the by-pass condenser, both being connected in parallel to the first feedback resistor, and both ends of the by-pass condenser, together with the second feedback resistor, can be connected to the inverting amplifier circuit via first and second switching devices.

Abstract: A semiconductor integrated circuit device in which an internal circuit thereof is held by a backup power source when a main power source is disconnected comprises a comparator 29 for comparing a potential at a first power terminal 111 with that at a second power terminal 110. When the potential at the first power terminal is reduced switch means 212 connected between the first and second power terminals is closed to supply power from the second power terminal to a data storage unit 17 while forbidding write and read operations of store data.

Abstract: A differential amplifying circuit includes a differential input portion, a load portion, a switching portion, and a constant current source. The differential input portion is connected to the constant current source, and includes a pair of field effect transistors (FETs), with one having a gate for receiving an input voltage, a source connected to the current source and a drain connected to a first node, and the other having a gate for receiving a reference voltage, a source connected to the current source and a drain connected to a second node. The load portion includes a pair of FETs, with one having a drain connected to a first power source and a source connected to a first output terminal, and the other having a drain connected to the first power source and a source connected to a second output terminal. The switching portion includes a pair of FETs, with one having a source connected to the first output terminal, and the other having a source connected to the second output terminal.

Abstract: An A/D converter has a transfer channel and a plurality of transfer electrodes for transferring a charge from the transfer channel in a predetermined direction. When the number of bits of the digital signal to be generated is n, the number of charge transfer stages is 2n. A ratio of the area of the last electrode of a given odd-numbered stage to that of the last electrode of the immediately preceding odd-numbered stage is 1:2. Each even-numbered transfer stage has a first transfer path for transferring a charge exceeding 1/2 of the channel potential of the last electrode of the immediately preceding stage and a second transfer path for transferring a charge which does not exceed 1/2 of the channel potential. The charge transferred to the first transfer path is detected. Transfer of the charge on the second transfer path to the next stage or sweeping thereof outside the charge transfer section is switched in accordance with the transfer charge detection signal.

Abstract: A signal detecting circuit includes a first source follower having an input connected to a first voltage source, and a second source follower having an input connected to a second voltage source. There is provided an additional field effect transistor having a gate connected to the input of the second source follower, a source which is connected through a resistor to an output of the first source follower. The source of the additional field effect transistor is connected to a signal input terminal and one input of a voltage comparator whose other input is connected to an output of the second source follower.