Abstract: A semiconductor device includes a plurality of first electrode films stacked in a first direction and electrically isolated from each other; a plurality of semiconductor members extending in the first direction through the plurality of first electrode films; a first conductive film including a first surface and connected to the plurality of semiconductor members on the first surface; a first insulating film spaced from the first conductive film on a second surface of the first conductive film opposite to the first surface; a first edge member disposed in an edge area that surrounds an element area including the first electrode film, the semiconductor member, and the first conductive film; and a conductive first plug provided between the first edge member and the element area in the edge area and is in contact with the first insulating film.

Abstract: A semiconductor device includes a first substrate, a first insulating film disposed on the first substrate, and a semiconductor layer disposed on the first insulating film. The semiconductor device further includes a metal layer with a first portion and a second portion. The first portion is disposed on the semiconductor layer, and the second portion includes a bonding pad and is disposed on the first insulating film without the semiconductor layer interposed between the second portion and the first insulating film.

Abstract: A semiconductor memory device of embodiments includes a semiconductor substrate having a first and a second region adjacent to the first region in a first direction, a laminated body including electrode layers laminated on the semiconductor substrate in a second direction, a first insulator splitting the laminated body at the second region in a third direction, and extending in the first and second direction, and branching into two insulator films at the first region, and enclosing continuously a first portion of the laminated body, a contact portion extending in the first portion in the second direction, and a memory portion extending through the laminated body and the first insulator in the second direction at the second region. A first width in the third direction of the first portion is wider than a second width in the third direction of at least one of the electrode layers at the second region.

Abstract: A semiconductor memory device includes a plurality of first conductor layers that are stacked in a first direction; a first pillar including a first semiconductor layer and extending through the first conductor layers in the first direction; a first charge storage layer that is provided between the first conductor layers and the first semiconductor layer; a plurality of second conductor layers that are stacked in the first direction above an uppermost conductor layer of the first conductor layers; a second pillar including a second semiconductor layer and extending through the second conductor layers in the first direction, the second semiconductor layer electrically connected to the first semiconductor layer; and a conductor pillar or film extending in the first direction through the second conductor layers other than a lowermost layer of the second conductor layers and being in contact with a respective upper surface of each of the second conductor layers.

Abstract: A semiconductor memory device includes a plurality of first conductor layers that are stacked in a first direction; a first pillar including a first semiconductor layer and extending through the first conductor layers in the first direction; a first charge storage layer that is provided between the first conductor layers and the first semiconductor layer; a plurality of second conductor layers that are stacked in the first direction above an uppermost conductor layer of the first conductor layers; a second pillar including a second semiconductor layer and extending through the second conductor layers in the first direction, the second semiconductor layer electrically connected to the first semiconductor layer; and a conductor pillar or film extending in the first direction through the second conductor layers other than a lowermost layer of the second conductor layers and being in contact with a respective upper surface of each of the second conductor layers.

Abstract: A semiconductor memory device of embodiments includes a semiconductor substrate having a first and a second region adjacent to the first region in a first direction, a laminated body including electrode layers laminated on the semiconductor substrate in a second direction, a first insulator splitting the laminated body at the second region in a third direction, and extending in the first and second direction, and branching into two insulator films at the first region, and enclosing continuously a first portion of the laminated body, a contact portion extending in the first portion in the second direction, and a memory portion extending through the laminated body and the first insulator in the second direction at the second region. A first width in the third direction of the first portion is wider than a second width in the third direction of at least one of the electrode layers at the second region.

Abstract: A memory device includes a memory region, a connection region, an interconnection layer and a circuit. The memory region includes electrode layers and semiconductor layers. The electrode layers are stacked in a first direction, and the semiconductor layers extend in the first direction through the electrode layers. The connection region is surrounded with the memory region, and includes an insulating body and contact plugs. The insulating body has a thickness in the first direction thicker than a stacked width in the first direction of the electrode layers, and the contact plugs extending in the first direction through the insulating body. The interconnection layer includes interconnections electrically connected respectively to the electrode layers and some of the semiconductor layers. The electrode layers and the insulating body are positioned between the circuit and the interconnection layer in the first direction.

Abstract: A semiconductor device according to an embodiment includes first conductors, first pillars, a pillar column. Each of the first pillars is provided through the first conductors. The pillar column includes second pillars that are aligned in a first direction. Each of the second pillars is provided through the first conductors. The pillar column includes first and second columns of the second pillars. The first and second columns of the second pillars are aligned in a second direction that intersects the first direction. The first pillars are arranged on both sides in the second direction of each pillar column. The first conductors are provided continuously on both sides in the second direction of the second pillars that are included in each pillar column.

Abstract: A memory device includes a memory region, a connection region, an interconnection layer and a circuit. The memory region includes electrode layers and semiconductor layers. The electrode layers are stacked in a first direction, and the semiconductor layers extend in the first direction through the electrode layers. The connection region is surrounded with the memory region, and includes an insulating body and contact plugs. The insulating body has a thickness in the first direction thicker than a stacked width in the first direction of the electrode layers, and the contact plugs extending in the first direction through the insulating body. The interconnection layer includes interconnections electrically connected respectively to the electrode layers and some of the semiconductor layers. The electrode layers and the insulating body are positioned between the circuit and the interconnection layer in the first direction.

Abstract: A method for manufacturing a semiconductor memory device includes forming a first insulating layer on a conductive layer; forming a second insulating layer on the first insulating layer, the second insulating layer including a first layer and a second layer having nitrogen and hydrogen bonds with higher density than a density thereof in the first layer; forming a third insulating layer on the second insulating layer; forming a semiconductor layer extending through the first insulating layer and the second insulating layer in a direction toward the third insulating layer from the conductive layer; selectively removing the second insulating layer to form a space, the first insulating layer being exposed in the space; forming the fourth insulating layer between the conductive layer and the first insulating layer, the fourth insulating layer being formed by thermally oxidizing the conductive layer through the first insulating layer in the space.

Abstract: A method for manufacturing a semiconductor memory device includes forming a first insulating layer on a conductive layer; forming a second insulating layer on the first insulating layer, the second insulating layer including a first layer and a second layer having nitrogen and hydrogen bonds with higher density than a density thereof in the first layer; forming a third insulating layer on the second insulating layer; forming a semiconductor layer extending through the first insulating layer and the second insulating layer in a direction toward the third insulating layer from the conductive layer; selectively removing the second insulating layer to form a space, the first insulating layer being exposed in the space; forming the fourth insulating layer between the conductive layer and the first insulating layer, the fourth insulating layer being formed by thermally oxidizing the conductive layer through the first insulating layer in the space.

Abstract: According to an embodiment, a semiconductor memory device comprises: a memory string comprising memory cells; and a contact electrically connected to one end of the memory string. The memory string comprises: control gate electrodes stacked above a first semiconductor layer; a second semiconductor layer having one end connected to the first semiconductor layer and having as its longitudinal direction a direction perpendicular to the first semiconductor layer, the second semiconductor layer facing the control gate electrodes; and a charge accumulation layer positioned between the control gate electrode and the second semiconductor layer. The contact has a plate-like shape whose longitudinal direction is a first direction, the contact has its lower surface connected to the first semiconductor layer, and the contact has a height of at least part of its upper surface lower than a height of an upper surface of the second semiconductor layer.

Abstract: According to an embodiment, a semiconductor memory device comprises: a memory string comprising memory cells; and a contact electrically connected to one end of the memory string. The memory string comprises: control gate electrodes stacked above a first semiconductor layer; a second semiconductor layer having one end connected to the first semiconductor layer and having as its longitudinal direction a direction perpendicular to the first semiconductor layer, the second semiconductor layer facing the control gate electrodes; and a charge accumulation layer positioned between the control gate electrode and the second semiconductor layer. The contact has a plate-like shape whose longitudinal direction is a first direction, the contact has its lower surface connected to the first semiconductor layer, and the contact has a height of at least part of its upper surface lower than a height of an upper surface of the second semiconductor layer.

Abstract: A semiconductor device includes a plurality of parallel conductive lines that are spaced apart from one another in a first direction and extend in a second direction transverse to the first direction. The parallel conductive lines includes first and second lines that are adjacent, and a third line that is adjacent to the second line, and the first and third lines each have a cut portion at different points along the second direction.

Abstract: A semiconductor device includes a plurality of parallel conductive lines that are spaced apart from one another in a first direction and extend in a second direction transverse to the first direction. The parallel conductive lines includes first and second lines that are adjacent, and a third line that is adjacent to the second line, and the first and third lines each have a cut portion at different points along the second direction.

Abstract: According to one embodiment, a semiconductor memory device includes a substrate, an upper-layer wire provided on the substrate, a lower-layer wire provided on the substrate, a memory cell located at an intersection of the upper-layer wire and the lower-layer wire and includes a diode and a storage layer, a conductive layer located between the upper-layer wire and the memory cell in a direction perpendicular to the substrate surface, and an interlayer insulating film provided between memory cells. The position of an interface between the upper-layer wire and the interlayer insulating film is lower than a top surface of the conductive layer.

Abstract: A semiconductor storage device according to the present embodiment includes a semiconductor substrate. A plurality of memory cells are provided on the semiconductor substrate. Peripheral circuits are provided on a periphery of the memory cells. A first barrier film includes a first nitride film provided on a first gate electrode of a transistor included in the peripheral circuits. A second barrier film includes a second nitride film different from the first nitride film. The second nitride film is provided on a second gate electrode of the memory cells, respectively. Metal layers are provided on the first and second barrier films, respectively.

Abstract: According to one embodiment, a semiconductor memory device includes a substrate, an upper-layer wire provided on the substrate, a lower-layer wire provided on the substrate, a memory cell located at an intersection of the upper-layer wire and the lower-layer wire and includes a diode and a storage layer, a conductive layer located between the upper-layer wire and the memory cell in a direction perpendicular to the substrate surface, and an interlayer insulating film provided between memory cells. The position of an interface between the upper-layer wire and the interlayer insulating film is lower than a top surface of the conductive layer.

Abstract: According to one embodiment, a semiconductor memory device includes a substrate, an upper-layer wire provided on the substrate, a lower-layer wire provided on the substrate, a memory cell located at an intersection of the upper-layer wire and the lower-layer wire and includes a diode and a storage layer, a conductive layer located between the upper-layer wire and the memory cell in a direction perpendicular to the substrate surface, and an interlayer insulating film provided between memory cells. The position of an interface between the upper-layer wire and the interlayer insulating film is lower than a top surface of the conductive layer.

Abstract: The present invention relates to methods of fabricating semiconductor devices, including forming a trench in a semiconductor substrate by a reactive ion etching (RIE) method with a reactive product of film stack of a carbon film/silicon oxide film/carbon-containing silicon oxide film, the trench having an inner surface; and removing the reactive product, by treating the trench with diluted hydrofluoric acid to remove the carbon film and the silicon oxide film followed by treating the film by a hydrofluoric acid vapor phase cleaning (HFVPC) method to remove the carbon-containing silicon oxide film.