Patents by Inventor Masahisa Suzuki
Masahisa Suzuki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240128081Abstract: A film forming method includes preparing a substrate having an amorphous silicon film on a surface thereof, diffusing nickel into the amorphous silicon film by supplying a nickel source gas to the amorphous silicon film, and forming a polycrystalline silicon film by heating the amorphous silicon film, and crystallizing the amorphous silicon film by metal-induced lateral crystallization using the nickel diffused in the amorphous silicon film as a nucleus.Type: ApplicationFiled: October 5, 2023Publication date: April 18, 2024Inventors: Yoshihiro TAKEZAWA, Toru KANAZAWA, Yosuke WATANABE, Tatsuya MIYAHARA, Yuki TANABE, Daisuke SUZUKI, Masahisa WATANABE, Keisuke SUZUKI, Tuhin Shuvra Basu
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Patent number: 6217375Abstract: A wiring harness arranging construction is provided to arrange a wiring harness in a position more toward a passenger compartment than a hinge and a weatherstrip. The construction includes a container casing 10 with a space 10p for accommodating a looped harness, an insertion opening 10f and a withdrawal opening 10g for the harness which are opposed to each other, and a harness fixing portion 10h projecting from the outer surface of the insertion opening 10f. After being inserted through the insertion opening 10f and wound around a windup spring 30 inside the casing 10, the wiring harness is withdrawn through the withdrawal opening 10g. The container casing 10 is secured to either one of a door and a body, and the wiring harness withdrawn from the container casing 10 is extended to the other of the door and the body and secured thereto by a clamp.Type: GrantFiled: April 19, 1999Date of Patent: April 17, 2001Assignee: Sumitomo Wiring Systems, Ltd.Inventors: Satoshi Nagai, Tetuya Funaki, Masahisa Suzuki, Yasuhiro Ando, Shinya Miyamoto
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Patent number: 6107570Abstract: There is provided a guide frame 10 having a small width and a triangular or other shape. An insertion opening 10e and a withdrawal opening 10g for a wiring harness D.multidot.W/H are formed in spaced-apart positions of the guide frame 10. The wiring harness D.multidot.W/H is fixedly inserted through the insertion opening 10e of the guide frame 10 and withdrawn through the withdrawal opening 10g after being arranged in a roundabout manner inside the guide frame 10. The guide frame 10 is fixed to either one of a door D and a body C, and the leading end of the wiring harness D.multidot.W/H withdrawn from the guide frame 10 through the withdrawal opening 10g is extended to the other of the door D and the body C, so that the wiring harness D.multidot.W/H comes from and returns into the guide frame 10 according to opening and closing movements of the door D.Type: GrantFiled: June 16, 1999Date of Patent: August 22, 2000Assignee: Sumitomo Wiring Systems, Ltd.Inventors: Masahisa Suzuki, Tetsuya Takimoto, Yasuhiro Ando, Tetuya Funaki, Shinichi Suehiro
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Patent number: 6079764Abstract: A guide member 10 made of an elastic material has an arcuate portion 10a which extends and contracts while twisting. A wiring harness D.multidot.W/H is arranged between a door and a body of a vehicle after being mounted on the guide member 10, and the opposite ends of the guide member 10 are fixed to the door and the body, so that the movements of the guide member and the wiring harness can follow the opening and closing movements of the door. The arcuate portion 10a is so configured as to construct a part of a torsion coil spring.Type: GrantFiled: June 9, 1997Date of Patent: June 27, 2000Assignee: Sumitomo Wiring Systems, Ltd.Inventors: Masahisa Suzuki, Tetsuya Takimoto, Yasuhiro Ando, Tetuya Funaki, Shinichi Suehiro
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Patent number: 5994645Abstract: There is provided a guide frame 10 having a small width and a triangular or other shape. An insertion opening 10e and a withdrawal opening 10g for a wiring harness DW/H are formed in spaced-apart positions of the guide frame 10. The wiring harness DW/H is fixedly inserted through the insertion opening 10e of the guide frame 10 and withdrawn through the withdrawal opening 10g after being arranged in a roundabout manner inside the guide frame 10. The guide frame 10 is fixed to either one of a door D and a body C, and the leading end of the wiring harness DW/H withdrawn from the guide frame 10 through the withdrawal opening 10g is extended to the other of the door D and the body C, so that the wiring harness D.multidot.W/H comes from and returns into the guide frame 10 according to opening and closing movements of the door D.Type: GrantFiled: June 9, 1997Date of Patent: November 30, 1999Assignee: Sumitomo Wiring Systems, Ltd.Inventors: Masahisa Suzuki, Tetsuya Takimoto, Yasuhiro Ando, Tetuya Funaki, Shinichi Suehiro
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Patent number: 5957702Abstract: A wiring harness arranging construction is provided to arrange a wiring harness in a position more toward a passenger compartment than a hinge and a weatherstrip. The construction includes a container casing 10 with a space 10p for accommodating a looped harness, an insertion opening 10f and a withdrawal opening 10g for the harness which are opposed to each other, and a harness fixing portion 10h projecting from the outer surface of the insertion opening 10f. After being inserted through the insertion opening 10f and wound around a windup spring 30 inside the casing 10, the wiring harness is withdrawn through the withdrawal opening 10g. The container casing 10 is secured to either one of a door and a body, and the wiring harness withdrawn from the container casing 10 is extended to the other of the door and the body and secured thereto by a clamp.Type: GrantFiled: December 23, 1997Date of Patent: September 28, 1999Assignee: Sumitomo Wiring Systems, Ltd.Inventors: Satoshi Nagai, Tetuya Funaki, Masahisa Suzuki, Yasuhiro Ando, Shinya Miyamoto
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Patent number: 5358900Abstract: A semiconductor device includes a semiconductor substrate, an active layer formed on the semiconductor substrate, source and drain electrodes respectively formed on the active layer, a gate electrode formed on the active layer between the source and drain electrodes and including a gate contact portion which makes contact with the active layer and has a thickness greater than those of the source and drain electrodes and an overgate portion which is connected to the gate contact portion and extends over at least a portion of one of the source and drain electrodes, a first insulator layer formed on the active layer and covering the source and drain electrodes and the gate contact portion, a first contact hole in the first insulator layer through which the overgate portion connects to the one of the source and drain electrodes, a second insulator layer formed on the first insulator layer and covering the overgate portion, a second contact hole in the second insulator layer at a position above the overgate portioType: GrantFiled: July 13, 1993Date of Patent: October 25, 1994Assignee: Fujitsu LimitedInventor: Masahisa Suzuki
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Patent number: 5276340Abstract: A semiconductor integrated circuit including therein a plurality of active devices comprises a semiconductor substrate, a first buffer layer on the substrate, a second buffer layer provided on the substrate and incorporating therein defects with a concentration level substantially larger than the concentration level of the defects in the first buffer layer; a device layer provided on the second buffer layer and being provided with the active devices, and a plurality of unconductive, device isolation regions formed between the active devices such that the device isolation region extends from an upper surface of the device layer toward the substrate at least beyond a lower surface of the device layer.Type: GrantFiled: November 13, 1992Date of Patent: January 4, 1994Assignee: Fujitsu LimitedInventors: Teruo Yokoyama, Masahisa Suzuki, Tomonori Ishikawa, Takeshi Igarashi
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Patent number: 5252843Abstract: A semiconductor device includes a semiconductor substrate, an active layer formed on the semiconductor substrate, source and drain electrodes respectively formed on the active layer, a gate electrode formed on the active layer between the source and drain electrodes and including a gate contact portion which makes contact with the active layer and has a thickness greater than those of the source and drain electrodes and an overgate portion which is connected to the gate contact portion and extends over at least a portion of one of the source and drain electrodes, a first insulator layer formed on the active layer and covering the source and drain electrodes and the gate contact portion, a first contact hole in the first insulator layer through which the overgate portion connects to the one of the source and drain electrodes, a second insulator layer formed on the first insulator layer and covering the overgate portion, a second contact hole in the second insulator layer at a position above the overgate portioType: GrantFiled: December 16, 1991Date of Patent: October 12, 1993Assignee: Fujitsu LimitedInventor: Masahisa Suzuki
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Patent number: 4615102Abstract: A semiconductor device, which comprises an E-mode FET and a D-mode FET and utilizes a two-dimensional electron gas, comprises a semi-insulating semiconductor substrate, a channel layer, an electron-supply layer, a third layer, a first etching-stoppable layer, a fifth layer, and a second etching-stoppable layer, which layers are formed in sequence on the substrate. An etching process for forming grooves of gate electrodes of the FETs comprises a first etching treatment removing the first etching-stoppable layer portion in the E-mode FET region and the second etching-stoppable layer portion in the D-mode FET region, and a second etching treatment removing the third layer portion in the E-mode FET region and the fifth layer portion and using an etchant different from that used in the first etching treatment. In the second etching treatment, reactive ion etching method using a CCl.sub.2 F.sub.Type: GrantFiled: April 29, 1985Date of Patent: October 7, 1986Assignee: Fujitsu LimitedInventors: Masahisa Suzuki, Takashi Mimura
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Patent number: D397092Type: GrantFiled: January 3, 1997Date of Patent: August 18, 1998Assignee: Fujitsu LimitedInventors: Yoshiaki Sano, Takashi Yoshida, Takahisa Kawai, Masahisa Suzuki