Abstract: A semiconductor integrated circuit has a scan chain with a scan clock signal line for clocking scan flip-flops and a scan test signal line for transferring scanning data into and out of the scan flip-flops. Part of the scan test signal line is routed adjacently parallel to the scan clock signal line to shield the scan clock signal line from electrical noise during normal operation, when the scan test signal line is held at a fixed potential. Separate shield lines are used to shield parts of the scan clock signal line not shielded by the scan test signal line. Use of a combination of shield lines and the scan test signal line to shield the scan clock signal line saves space and conserves routing resources.

Abstract: An integrated circuit has a capacitor consisting of an active area originally employable for power supply/GND, a gate insulator layer and a conductive polycrystalline silicon layer produced on a part of the active area originally employable for power supply/GND. The capacitor is employed to exclude external noises from the integrated circuit and is produced on an area which is unemployed in the prior art.

Abstract: A chip layout of a semiconductor integrated circuit, includes a plurality of device patterns that are designed to form a semiconductor substrate having a single power supply; and a metal wiring pattern, which is to be formed on the semiconductor substrate. The metal wiring pattern is divided into plural parts to provide a plurality of power-supply channels.