Patents by Inventor Masahisa Ueda
Masahisa Ueda has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10619261Abstract: A manufacturing method for an electronic component according to an aspect of the present invention includes: forming a first metal layer on a substrate; forming a second metal layer on the first metal layer; forming a mask made of an organic resin layer on the second metal layer; performing plasma etching on the second metal layer by using a reactant gas including fluorine via the mask to thereby form a recess portion in a layered film of the organic resin layer and the second metal layer; performing oxygen ashing treatment on an inner surface of the recess portion; and forming a third metal layer in the recess portion by electroplating treatment after the oxygen ashing treatment.Type: GrantFiled: March 22, 2018Date of Patent: April 14, 2020Assignee: ULVAC, INC.Inventors: Daisuke Hironiwa, Takashi Kurimoto, Masahisa Ueda
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Patent number: 10537514Abstract: A hair color which achieves excellent texture consistently from during plain rinsing in the treatment with the hair color to the dry state after the treatment is provided includes a hair cosmetic composition containing (A) one or more cationic polymers, (B) one or more cationic surfactants with a counter ion which is chlorine or an alkyl sulfate, (C) one or more selected from hydrocarbon oils, ester oils, waxes and vegetable oils, (D) one or more nonionic surfactants and (E) one or more selected from oleyl alcohol and oleic acid.Type: GrantFiled: October 31, 2016Date of Patent: January 21, 2020Assignee: HOYU CO., LTD.Inventors: Masahisa Ueda, Akihiro Inui, Yuriko Kozu
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Publication number: 20190177865Abstract: A manufacturing method for an electronic component according to an aspect of the present invention includes: forming a first metal layer on a substrate; forming a second metal layer on the first metal layer; forming a mask made of an organic resin layer on the second metal layer; performing plasma etching on the second metal layer by using a reactant gas including fluorine via the mask to thereby form a recess portion in a layered film of the organic resin layer and the second metal layer; performing oxygen ashing treatment on an inner surface of the recess portion; and forming a third metal layer in the recess portion by electroplating treatment after the oxygen ashing treatment.Type: ApplicationFiled: March 22, 2018Publication date: June 13, 2019Inventors: DAISUKE HIRONIWA, TAKASHI KURIMOTO, MASAHISA UEDA
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Publication number: 20170119648Abstract: A hair color which achieves excellent texture consistently from during plain rinsing in the treatment with the hair color to the dry state after the treatment is provided includes a hair cosmetic composition containing (A) one or more cationic polymers, (B) one or more cationic surfactants with a counter ion which is chlorine or an alkyl sulfate, (C) one or more selected from hydrocarbon oils, ester oils, waxes and vegetable oils, (D) one or more nonionic surfactants and (E) one or more selected from oleyl alcohol and oleic acid.Type: ApplicationFiled: October 31, 2016Publication date: May 4, 2017Inventors: Masahisa UEDA, Akihiro INUI, Yuriko KOZU
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Patent number: 9466475Abstract: An ashing device that prevents the ashing rate from changing over time. The ashing device ashes organic material on a substrate including an exposed metal in a processing chamber. The ashing device includes a path, which is formed in the processing chamber and through which active species supplied to the processing chamber pass. The path is defined by a surface on which the metal scattered from the substrate by the active species is collectible, with the surface being formed so as to expose a metal that is of the same kind.Type: GrantFiled: September 26, 2014Date of Patent: October 11, 2016Assignee: ULVAC, INC.Inventors: Masahisa Ueda, Takashi Kurimoto, Kyuzo Nakamura, Koukou Suu, Toshiya Yogo, Kazushige Komatsu, Nobusuke Tachibana
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Patent number: 9305752Abstract: A method for operating a substrate processing apparatus is provided which can contain generation of particles by generating plasma in a stable manner. After a substrate is disposed in an evacuated vacuum chamber, a rare gas is initially supplied into the vacuum chamber, a voltage is applied to a plasma generating means, and plasma of the rare gas is generated. Subsequently, a reaction gas is supplied into the vacuum chamber, the reaction gas is brought into contact with the plasma of the rare gas, and plasma of the reaction gas is generated. The plasma of the reaction gas is brought into contact with the substrate; and the substrate is processed. Plasma is stably generated not by turning the reaction gas into plasma but by first turning the rare gas into plasma by the plasma generating means, and generation of particles is subsequently suppressed.Type: GrantFiled: March 8, 2012Date of Patent: April 5, 2016Assignee: ULVAC, INC.Inventors: Yutaka Kokaze, Masahisa Ueda, Yoshiaki Yoshida
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Patent number: 9059105Abstract: Disclosed is an ashing apparatus and its method of manufacture wherein decrease in processing efficiency is suppressed. Specifically, a shower plate is arranged to face a substrate stage on which a substrate is placed, and diffuses oxygen radicals supplied into a chamber. A metal blocking plate is arranged between the shower plate and the substrate stage and has a through hole through which oxygen radicals pass. In addition, the metal blocking plate has a first layer, which is made of a metal same as the one exposed in the substrate, on the surface facing the substrate.Type: GrantFiled: December 26, 2007Date of Patent: June 16, 2015Assignee: Ulvac, Inc.Inventors: Masahisa Ueda, Takashi Kurimoto, Michio Ishikawa, Koukou Suu, Toshiya Yogo
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Publication number: 20150013715Abstract: An ashing device that prevents the ashing rate from changing over time. The ashing device ashes organic material on a substrate including an exposed metal in a processing chamber. The ashing device includes a path, which is formed in the processing chamber and through which active species supplied to the processing chamber pass. The path is defined by a surface on which the metal scattered from the substrate by the active species is collectible, with the surface being formed so as to expose a metal that is of the same kind.Type: ApplicationFiled: September 26, 2014Publication date: January 15, 2015Inventors: Masahisa Ueda, Takashi Kurimoto, Kyuzo Nakamura, Koukou Suu, Toshiya Yogo, Kazushige Komatsu, Nobusuke Tachibana
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Publication number: 20120193323Abstract: A method for operating a substrate processing apparatus is provided which can contain generation of particles by generating plasma in a stable manner. After a substrate is disposed in an evacuated vacuum chamber, a rare gas is initially supplied into the vacuum chamber, a voltage is applied to a plasma generating means, and plasma of the rare gas is generated. Subsequently, a reaction gas is supplied into the vacuum chamber, the reaction gas is brought into contact with the plasma of the rare gas, and plasma of the reaction gas is generated. The plasma of the reaction gas is brought into contact with the substrate; and the substrate is processed. Plasma is stably generated not by turning the reaction gas into plasma but by first turning the rare gas into plasma by the plasma generating means, and generation of particles is subsequently suppressed.Type: ApplicationFiled: March 8, 2012Publication date: August 2, 2012Applicant: ULVAC, INC.Inventors: Yutaka KOKAZE, Masahisa Ueda, Yoshiaki Yoshida
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Publication number: 20120152889Abstract: A method for manufacturing a piezoelectric element, in which a ferroelectric film is processed in an appropriate shape by plasma etching, is provided. A metal mask made of a metal thin film which is hard to be etched by oxygen gas is placed on an object to be processed formed by laminating a lower electrode layer and a ferroelectric film on a substrate in this order. An etching gas containing a mixture gas of the oxygen gas and a reactive gas including fluorine in a chemical structure is turned into plasma and is brought into contact with the metal mask and the object to be processed. An AC voltage is applied to an electrode disposed beneath the object to be processed so that ions in the plasma are caused to enter the object to be processed to perform anisotropic etching on the ferroelectric film.Type: ApplicationFiled: February 3, 2012Publication date: June 21, 2012Applicant: ULVAC. INC.Inventors: Masahisa Ueda, Yoshiaki Yoshida, Yutaka Kokaze
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Patent number: 8133325Abstract: This dry cleaning method for a plasma processing apparatus is a dry cleaning method for a plasma processing apparatus that includes: a vacuum container provided with a dielectric member; a planar electrode and a high-frequency antenna that are provided outside the dielectric member; and a high-frequency power source that supplies high-frequency power to both the high-frequency antenna and the planar electrode, to thereby introduce high-frequency power into the vacuum container via the dielectric member and produce an inductively-coupled plasma, the method comprising the steps of: introducing a gas including fluorine into the vacuum container and also introducing high-frequency power into the vacuum container from the high-frequency power source, to thereby produce an inductively-coupled plasma in the gas including fluorine; and by use of the inductively-coupled plasma, removing a product including at least one of a precious metal and a ferroelectric that is adhered to the dielectric member.Type: GrantFiled: May 28, 2008Date of Patent: March 13, 2012Assignee: ULVAC, Inc.Inventors: Masahisa Ueda, Yutaka Kokaze, Mitsuhiro Endou, Koukou Suu
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Publication number: 20100213170Abstract: An etching method which uses an apparatus having a chamber in which an etching gas is excited by plasma; a table arranged in the chamber which heats a substrate mounted thereon; and a frame member which includes etching-endurable material which is arranged around the table, and which has an upper surface arranged at a position lower than an upper surface of the table, the etching method including: arranging the substrate on the upper surface of the table such that a peripheral part of the substrate projects above the table; and arranging the substrate such that a ratio of a height from the upper surface of the frame member to a bottom surface of the substrate and a projecting length from a side surface of the table to an outer circumference of the substrate is 1.Type: ApplicationFiled: June 19, 2008Publication date: August 26, 2010Applicant: ULVAC, INC.Inventors: Yutaka Kokaze, Mitsuhiro Endou, Masahisa Ueda, Koukou Suu, Toshiya Miyazaki, Toshiyuki Nakamura
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Publication number: 20100193131Abstract: An ashing device that prevents the ashing rate from changing over time. The ashing device ashes organic material on a substrate including an exposed metal in a processing chamber. The ashing device includes a path, which is formed in the processing chamber and through which active species supplied to the processing chamber pass. The path is defined by a surface on which the metal scattered from the substrate by the active species is collectible, with the surface being formed so as to expose a metal that is of the same kind.Type: ApplicationFiled: October 29, 2008Publication date: August 5, 2010Applicant: ULVAC, INC.Inventors: Masahisa Ueda, Takashi Kurimoto, Kyuzo Nakamura, Koukou Suu, Toshiya Yogo, Kazushige Komatsu, Nobusuke Tachibana
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Publication number: 20100151150Abstract: A plasma processing apparatus of the present invention performs on a substrate to be processed, plasma processing with a noble metal material and a ferroelectric material and is provided with a constituent member that is exposed to plasma while being heated. The constituent member is formed with an aluminum alloy of at least 99% aluminum purity.Type: ApplicationFiled: May 14, 2008Publication date: June 17, 2010Applicant: ULVAC, INC.Inventors: Yutaka Kokaze, Masahisa Ueda, Mitsuhiro Endou, Koukou Suu, Toshiya Miyazaki, Genji Sakata, Toshiyuki Nakamura
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Publication number: 20100089533Abstract: Disclosed is an ashing apparatus wherein decrease in processing efficiency is suppressed. Specifically, a shower plate is arranged to face a substrate stage on which a substrate is placed, and diffuses oxygen radicals supplied into a chamber. A metal blocking plate is arranged between the shower plate and the substrate stage and has a through hole through which oxygen radicals pass. In addition, the metal blocking plate has a first layer, which is made of a metal same as the one exposed in the substrate, on the surface facing the substrate.Type: ApplicationFiled: December 26, 2007Publication date: April 15, 2010Applicant: ULVAC, INC.Inventors: Masahisa Ueda, Takashi Kurimoto, Michio Ishikawa, Koukou Suu, Toshiya Yogo
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Publication number: 20100083981Abstract: This dry cleaning method for a plasma processing apparatus is a dry cleaning method for a plasma processing apparatus that includes: a vacuum container provided with a dielectric member; a planar electrode and a high-frequency antenna that are provided outside the dielectric member; and a high-frequency power source that supplies high-frequency power to both the high-frequency antenna and the planar electrode, to thereby introduce high-frequency power into the vacuum container via the dielectric member and produce an inductively-coupled plasma, the method comprising the steps of: introducing a gas including fluorine into the vacuum container and also introducing high-frequency power into the vacuum container from the high-frequency power source, to thereby produce an inductively-coupled plasma in the gas including fluorine; and by use of the inductively-coupled plasma, removing a product including at least one of a precious metal and a ferroelectric that is adhered to the dielectric member.Type: ApplicationFiled: May 28, 2008Publication date: April 8, 2010Applicant: ULVAC, INC.Inventors: Masahisa Ueda, Yutaka Kokaze, Mitsuhiro Endou, Koukou Suu
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Publication number: 20090275146Abstract: A method for manufacturing a device, includes: (A) forming a first electrode layer on a substrate; (B) forming a ferroelectric layer on the first electrode layer; (C) forming a second electrode layer on the ferroelectric layer; (D) forming a mask having a predetermined pattern on the second electrode layer; (E) forming a memory element by selectively removing the first electrode layer, the ferroelectric layer, and the second electrode layer using the mask; and (F) removing the mask, where at least, the processes (D) and (E), or the processes (E) and (F) are continuously performed under a reduced pressure.Type: ApplicationFiled: April 22, 2009Publication date: November 5, 2009Applicants: ULVAC, Inc., Seiko Epson CorporationInventors: Katsuo TAKANO, Takeshi KOKUBUN, Yutaka KOKAZE, Masahisa UEDA, Mitsuhiro ENDOU, Koukou SUU, Toshiya MIYAZAKI, Toshiyuki NAKAMURA
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Publication number: 20080026539Abstract: An etching technique suitable for miniaturization is provided. An inorganic film is formed on an object to be subjected, the object having a lower electrode film, a dielectric film, and an upper electrode film laminated in that order on a substrate. A patterned organic resist film is disposed on the surface of the inorganic film. The inorganic film, upper electrode film, and the dielectric film are etched using the organic resist film as a mask, and then, the organic resist film is removed with the gas used to etch the lower electrode film; and the lower electrode film is etched using the inorganic film as a mask that has been exposed. Since the film serving as a mask is not re-formed, a fine pattern can be produced with good precision.Type: ApplicationFiled: July 20, 2007Publication date: January 31, 2008Applicant: ULVAC, INC.Inventors: Yutaka Kokaze, Masahisa Ueda, Mitsuhiro Endo, Koukou Suu
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Publication number: 20030071294Abstract: A method for fabricating integrated capacitors, of particular utility in forming a ferroelectric capacitor array for a ferroelectric memory integrated circuits, begins with provision of a substrate. The substrate is typically a partially-processed CMOS integrated circuit wafer coated with an adhesion layer. Upon the substrate is deposited a bottom electrode layer, typically of noble metal, a dielectric layer, typically doped PZT, and a top electrode layer, typically a noble metal oxide. Next is deposited a hardmask layer of strontium ruthenium oxide, followed by a photoresist layer. The photoresist layer is aligned, exposed, developed, and cured as known in the art of integrated circuit photolithography. The resulting stack is then dry etched to remove undesired portions of the hardmask layer, the top electrode layer, and the dielectric layer. A principle advantage of the process is that a single photomasking operation is sufficient to define the top electrode and dielectric layers.Type: ApplicationFiled: October 30, 2002Publication date: April 17, 2003Inventors: Shan Sun, George Hickert, Diana Johnson, John Ortega, Eric Dale, Masahisa Ueda
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Patent number: 6495413Abstract: A method for fabricating integrated capacitors, of particular utility in forming a ferroelectric capacitor array for a ferroelectric memory integrated circuits, begins with provision of a substrate. The substrate is typically a partially-processed CMOS integrated circuit wafer coated with an adhesion layer. Upon the substrate is deposited a bottom electrode layer, typically of noble metal, a dielectric layer, typically doped PZT, and a top electrode layer, typically a noble metal oxide. Next is deposited a hardmask layer of strontium ruthenium oxide, followed by a photoresist layer. The photoresist layer is aligned, exposed, developed, and cured as known in the art of integrated circuit photolithography. The resulting stack is then dry etched to remove undesired portions of the hardmask layer, the top electrode layer, and the dielectric layer. A principle advantage of the process is that a single photomasking operation is sufficient to define the top electrode and dielectric layers.Type: GrantFiled: February 28, 2001Date of Patent: December 17, 2002Assignees: Ramtron International Corporation, Ulvac Japan, Ltd.Inventors: Shan Sun, George Hickert, Diana Johnson, John Ortega, Eric Dale, Masahisa Ueda