Patents by Inventor Masahito Ishii

Masahito Ishii has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11515436
    Abstract: A photovoltaic device includes: a p- or n-type semiconductor substrate; a p-type amorphous semiconductor film and an n-type amorphous semiconductor film on a first-face side; p-electrodes on the p-type amorphous semiconductor film; and n-electrodes on the n-type amorphous semiconductor film, wherein: the p-electrodes and the n-electrodes are arranged at intervals; the p-type amorphous semiconductor film surrounds the n-type amorphous semiconductor film in an in-plane direction of the semiconductor substrate; the n-type amorphous semiconductor film has an edge portion providing an overlapping region where the n-type amorphous semiconductor film overlaps the p-type amorphous semiconductor film; and the n-electrodes are disposed in areas of the n-type amorphous semiconductor film that are surrounded by the overlapping region.
    Type: Grant
    Filed: February 9, 2022
    Date of Patent: November 29, 2022
    Assignee: SHARP KABUSHIKI KAISHA
    Inventors: Teruaki Higo, Chikao Okamoto, Masamichi Kobayashi, Masahito Ishii, Takeshi Mori, Yuta Matsumoto
  • Publication number: 20220271178
    Abstract: A photovoltaic device includes: a p- or n-type semiconductor substrate; a p-type amorphous semiconductor film and an n-type amorphous semiconductor film on a first-face side; p-electrodes on the p-type amorphous semiconductor film; and n-electrodes on the n-type amorphous semiconductor film, wherein: the p-electrodes and the n-electrodes are arranged at intervals; the p-type amorphous semiconductor film surrounds the n-type amorphous semiconductor film in an in-plane direction of the semiconductor substrate; the n-type amorphous semiconductor film has an edge portion providing an overlapping region where the n-type amorphous semiconductor film overlaps the p-type amorphous semiconductor film; and the n-electrodes are disposed in areas of the n-type amorphous semiconductor film that are surrounded by the overlapping region.
    Type: Application
    Filed: February 9, 2022
    Publication date: August 25, 2022
    Inventors: TERUAKI HIGO, CHIKAO OKAMOTO, MASAMICHI KOBAYASHI, MASAHITO ISHII, TAKESHI MORI, YUTA MATSUMOTO
  • Publication number: 20190189811
    Abstract: A photovoltaic device includes: a p- or n-type semiconductor substrate; a p-type amorphous semiconductor film and an n-type amorphous semiconductor film on a first-face side; p-electrodes on the p-type amorphous semiconductor film; and n-electrodes on the n-type amorphous semiconductor film, wherein: the p-electrodes and the n-electrodes are arranged at intervals; the p-type amorphous semiconductor film surrounds the n-type amorphous semiconductor film in an in-plane direction of the semiconductor substrate; the n-type amorphous semiconductor film has an edge portion providing an overlapping region where the n-type amorphous semiconductor film overlaps the p-type amorphous semiconductor film; and the n-electrodes are disposed in areas of the n-type amorphous semiconductor film that are surrounded by the overlapping region.
    Type: Application
    Filed: August 14, 2017
    Publication date: June 20, 2019
    Inventors: TERUAKI HIGO, CHIKAO OKAMOTO, MASAMICHI KOBAYASHI, MASAHITO ISHII, TAKESHI MORI, YUTA MATSUMOTO
  • Publication number: 20090314525
    Abstract: A process for producing a wiring board is provided, comprising allowing a wiring board-forming mold, which comprises a support base and a mold pattern that is formed in a protruded shape on one surface of the support base wherein the sectional width of the mold pattern on the support base side is larger than the sectional width thereof on the tip side in the same section of the mold pattern, to penetrate into a curing resin layer to transfer the mold pattern, curing the curing resin layer, releasing the laminate from the mold, depositing a conductive metal, and polishing the deposited metal layer that to form a depressed wiring pattern, and a wiring board produced by this process.
    Type: Application
    Filed: May 31, 2006
    Publication date: December 24, 2009
    Applicant: MITSUI MINING & SMELTING CO., LTD.
    Inventors: Hitoshi Kajino, Takeo Taguchi, Kanji Sato, Masahito Ishii, Tatsuo Kataoka
  • Patent number: 7178233
    Abstract: A process for producing a printed wiring board-forming sheet comprising a resin sheet having a through hole in the thickness direction and a metal chip inserted in the through hole. The sheet is produced by placing a resin sheet and conductive metal sheet in this order on a die base having a die hole, performing punching from the conductive metal sheet side to form a punched hole in the conductive metal sheet and to form a punched hole in the resin sheet and inserting the punched conductive metal chip in the through hole of the resin sheet whereby the front and back surfaces of the sheet can be electrically connected to each other. If the conductive metal chip is so inserted that its tip protrudes from the surface of the sheet, and if a large number of such substrates are laminated, electrical connection in the thickness direction can readily be made by virtue of the protruded conductive metal chips and a multi-layer board can be readily produced.
    Type: Grant
    Filed: December 4, 2003
    Date of Patent: February 20, 2007
    Assignees: Mitsui Mining & Smelting Co., Ltd., Suzuki Co., Ltd.
    Inventors: Toshiyuki Nakamura, Hideto Tanaka, Akira Ichiryu, Motonobu Takahashi, Masahito Ishii, Daisuke Arai
  • Patent number: 6798048
    Abstract: A 2-metal layer TAB and a both-sided CSP.BGA tape having an insulating substrate and a wiring layer provided on at least both sides of the substrate, the substrate having evenly spaced sprocket holes on both width direction edges in the longitudinal direction thereof and also having through-holes formed with a punching press, and the through-holes being filled with a conductor by means of a punching press such that the conductor and the wiring layers are electrically connected, which is characterized by having round pilot holes between the sprocket holes formed in the longitudinal direction thereof; and a process of producing the same.
    Type: Grant
    Filed: May 13, 2002
    Date of Patent: September 28, 2004
    Assignees: Mitsui Mining & Smelting Company, Ltd., Suzuki Co., Ltd.
    Inventors: Akira Ichiryu, Tatsuo Kataoka, Hirokazu Kawamura, Katsuhiko Hayashi, Masahito Ishii
  • Publication number: 20040111882
    Abstract: A process for producing a printed wiring board-forming sheet comprising a resin sheet having a through hole in the thickness direction and a metal chip inserted in the through hole. The sheet is produced by placing a resin sheet and conductive metal sheet in this order on a die base having a die hole, performing punching from the conductive metal sheet side to form a punched hole in the conductive metal sheet and to form a punched hole in the resin sheet and inserting the punched conductive metal chip in the through hole of the resin sheet whereby the front and back surfaces of the sheet can be electrically connected to each other. If the conductive metal chip is so inserted that its tip protrudes from the surface of the sheet, and if a large number of such substrates are laminated, electrical connection in the thickness direction can readily be made by virtue of the protruded conductive metal chips and a multi-layer board can be readily produced.
    Type: Application
    Filed: December 4, 2003
    Publication date: June 17, 2004
    Inventors: Toshiyuki Nakamura, Hideto Tanaka, Akira Ichiryu, Motonobu Takahashi, Masahito Ishii, Daisuke Arai
  • Publication number: 20040099441
    Abstract: A printed circuit board comprising an insulating substrate, a through-hole formed in the insulating substrate, an implant material filling the through-hole, and a wiring pattern formed on both faces of the insulating substrate and electrically connected with the implant material, characterized in that one face of a conductor wiring layer wherein a bump penetrates from one face to the other face and protrudes is adhered to the insulating substrate so as to be electrically connected to the implant material. This bump conductor wiring layer of this printed circuit board has a large degree of freedom in forming a wiring pattern, through-hole, and bump and is unlike conventional handled separately from the insulating substrate. Therefore, the effect arises that this circuit board is the target of commercial trading by itself.
    Type: Application
    Filed: October 24, 2003
    Publication date: May 27, 2004
    Inventors: Akira Ichiryu, Katsuhiko Hayashi, Tatsuo Karaoka, Hirokazu Kawamura, Masahito Ishii
  • Publication number: 20020187334
    Abstract: A two-metal TAB tape, double-sided CSP tape, and BGA tape in which the tape has an insulating substrate and wiring layers at least on both sides of the insulating substrate, sprocket holes are made at regular intervals in the longitudinal direction along the edges in the direction of the width, through holes are made in the substrate by punching press, the through holes are filled with conductor by punching press, and the conductor is electrically connected to the wiring layers, characterized in that pilot round holes are made among the sprocket holes made in the longitudinal direction. Methods for producing such two-metal TAB tape, double-sided CSP tape, and BGA tape are disclosed.
    Type: Application
    Filed: May 13, 2002
    Publication date: December 12, 2002
    Inventors: Akira Ichiryu, Tatsuo Kataoka, Hirokazu Kawamura, Katsuhiko Hayashi, Masahito Ishii
  • Patent number: 5019944
    Abstract: This invention relates to a mounting substrate onto which components such as an IC chip are to be mounted, its production method, and a printed wiring board having a connector function suitable for a fine pitch and its connection method. Metal nodules are formed on conductors of connection portions by electrodeposition, or the like. Connection is made by fixing connection portions by an adhesive. Good conduction can be secured through the metal nodules and good insulation can be held between adjacent conductors.
    Type: Grant
    Filed: May 25, 1989
    Date of Patent: May 28, 1991
    Assignee: Mitsui Mining & Smelting Co., Ltd.
    Inventors: Masahito Ishii, Tatsuo Kataoka, Yoshitaka Tanaka